I have looked everywhere, the datasheet, the Xilinx website, digilent, etc. etc. and can't find anything! I was able to use the Adept tool to verify that my Cellular RAM is functioning correctly, but I just can't find any stock VHDL code as a controller to write data to and read data from it!! Help!!
Found this link but it's for asynchronous mode, which is not nearly fast enough:
http://embsi.blogspot.com/2013/01/how-to-use-cellular-ram-from-micron.html
Eventually found this on the Nexys 2 Digilent page:
http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2
under
"Onboard Memory controller reference design"
It's just a shame that this was not included with Nexys 3 details as it would have saved a lot of time!
Hopefully somebody else with this issue could at least find what I posted here and find it quickly...
Related
I am using a Cyclone V on a SoCKit board (link here) (provided by Terasic), connecting an HSMC-NET daughter card (link here) to it in order to create a system that can communicate using Ethernet while communication that is both transmitted and received goes through the FPGA - The problem is, I am having a really, really hard time getting this system to work using Altera's Triple Speed Ethernet core.
I am using Qsys to construct the system that contains the Triple Speed Ethernet core, instantiating it inside a VHDL wrapper that also contains an instantiation of a packet generator module, connected directly to the transmit Avalon-ST sink port of the TSE core and controlled through an Avalon-MM slave interface connected to a JTAG to Avalon Master bridge core which has it's master port exported to the VHDL wrapper as well.
Then, using System Console, I am configuring the Triple Speed Ethernet core as described in the core's user guide (link here) at section 5-26 (Register Initialization) and instruct the packet generator module (also using System Console) to start and generate Ethernet packets into the TSE core's transmit Avalon-ST sink interface ports.
Although having everything configured exactly as described in the core's user guide (linked above) I cannot get it to output anything on the MII/GMII output interfaces, neither get any of the statistics counters to increase or even change - clearly, I am doing something wrong, or missing something, but I just can't find out what exactly it is.
Can any one please, please help me with this?
Thanks ahead,
Itamar
Starting the basic checks,
Have you simulated it? It's not clear to me if you are just simulating or synthesizing.
If you haven't simulated, you really should. If it's not working in SIM, why would it ever work in real life.
Make sure you are using the QIP file to synthesize the design. It will automatically include your auto generated SDC constraints. You will still need to add your own PIN constraints, more on that later.
The TSE is fairly old and reliable, so the obvious first things to check are Clock, Reset, Power and Pins.
a.) Power is usually less of problem on devkits if you have already run the demo that came with the kit.
b.) Pins can cause a whole slew of issues if they are not mapped right on this core. I'll assume you are leveraging something from Terasic. It should define a pin for reset, input clock and signal standards. Alot of times, this goes in the .qsf file, and you also reference the QIP file (mentioned above) in here too.
c.) Clock & Reset is a more likely culprit in my mind. No activity on the interface is kind of clue. One way to check, is to route your clocks to spare pins and o-scope them and insure they are what you think they are. Similarly, if you may want to bring out your reset to a pin and check it. MAKE SURE YOU KNOW THE POLARITY and you haven't been using ~reset in some places and non-inverted reset in others.
Reconfig block. Some Altera chips and certain versions of Quartus require you to use a reconfig block to configure the XCVR. This doesn't seem like your issue to me because you say the GMII is flat lined.
I truly apologize if my question is too amateurish or has been asked before (I searched and couldn't find anything).
I am working on a big project with a PIC MCU (MPLAB), I picked up where someone else stopped and he has no documentation of his code, it's horrible to look at.
The main problem is that I can't find any records online for functions that appear on the code (i.e rdft, I know it performs FFT but I want to know more about parameters structure etc.).
Is there a good online source for library function for PIC?
Or am I missing something and it's pure C written for embedded systems?
Thanks for your help.
Amir
With the provided information I cannot help with your particular code.
But answering your question:
Is there a good online source for library function for PIC?
Yes there is you can find it in http://www.microchip.com/doclisting/SoftwareLib.aspx
Where it includes several libraries including some to preform FFT's.
Or am I missing something and it's pure C written for embedded systems?
Well the IC provides several peripherals for different functionalities (SPI,I2C,ADC's, etc..) some IC's also include DSP's where one can implement FFT's making use of dedicated hardware on the IC's.
In the Software Lib's from Microchip you can find several libraries that provide an abstraction layer to access such hardware.
Well it's not easy to answer your questions, but when I program some C-Code in MPLAB X, I have no libraries, for the MCU. Well I program some 8-Bit MCUs like the PIC18F4550 or the PIC18F46K20, etc... But you can use some standard libraries like math.h, strings.h or so to implement. But the rest like an I2C-Port or an RS232-Port I write by my self in small functions. For the 8-Bit MCUs, there are practically no libraries available from Microchip themselves, at least what I know. :-)
My tip for you: Tell us which Microcontroller it is (if it is an 8-Bit or so) and take a look at the data sheet of it. Also, you could make a copy on your desktop of the Code and try to clean it up (with tabs), that it looks readable to you.
Well I don't know how else I could help you. :-)
I am new to VHDL and FPGA. I have written a sample code which does EXOR of a and b and stores it in c. This code is in VHDL behavioral architecture. I am using Quartus 11.1+SP2-2.11.
I assigned pins say a to SW0, b to SW1 and c to LEDG0. Everything is compiling and there are no errors. I go to Tools->Programmer. I have my FPGA in RUN mode. Mode in Programmer is JTAG and hence the Hardware setup is USB-Blaster [PORT 0]. When I load the .sof file and Click "Start", the progress says "failed". I do not know why.
I tried to search everywhere, but all tutorials or links give the same explanation. I guess there are hardly any who encountered this problem. I want to know if I am missing something. I want to get my fundamentals right!
Are you by any chance using Linux? If you are make sure you've done this: http://www.alterawiki.com/wiki/Quartus_for_Linux#Setup_JTAG
There can be multiple reasons as to why the loading of .sof to FPGA fails. I figured out the following for my device. If any of you are beginners, please follow the same:
1) Make sure you have the data sheet of your device with you. I followed a tutorial and entered the device number they mentioned not the one I had.
2) Check for pin assignments. This is the most important. I found out the Pins used for various switches and LEDs in a consolidated document online.
3) If it still does not work, it is best to contact experts.
Is thee FPGA an Altera DE2? If yes, you can try with this file that works with the DE2 board so that you can know if it is your .sof file that needs to be changed. If the USB blaser appears in Quartus Programmer then most likely your driver is installed correctly and you should verify whether it is your .sof file that needs to change or something else.
I'm currently learning OpenCL and got some problems with my program ( running fine on GPU but not on CPU). So I wanted to try gDebugger. I'd like to know if it's possible to see the input data passed to the kernel in gDebugger and if so how can I see. I searched but couldn't get information. I hope you'll be able to help.
Take care.
Best regards,
Jacq
You can see the input and output buffers in the Textures and Buffers viewer.
P.S: gDEBugger was replaced by CodeXL (http://developer.amd.com/tools-and-sdks/heterogeneous-computing/codexl/). You will enjoy this one...
I am writing a kernel module and need to perform reads from an existing block device. (/dev/something).
Does anyone know of any other modules that do these that I can use as reference ?
Any pointers would be welcome
(Linux.2.6.30)
If you really absolutely must then use the filp_open, filp_close, vfs_read and vfs_write functions.
The description for for filp_open states "This is the helper to open a file from kernelspace if you really have to. But in generally you should not do this, so please move along, nothing to see here.."
There is an excellent article "Driving Me Nuts - Things You Never Should Do in the Kernel" at http://www.linuxjournal.com/article/8110
You can look at any hard disk device driver.