I understand there is an option to add compile-time macros/definitions to the Kconfig file that can be used in the code.
(For example, some definition of a constant, like a #define).
The Kconfig values are passed as Makefile defines. Also, all selected Kconfig values are put in a header file and passed to the assembler and 'C' code. So, you do not do this directly in the Kconfig file, but can do it in the Makefile or source.
Kconfig
config MY_DEFINE
bool "Select to get some DEFINE"
default y
help
This is a config define that is sent to both make
and defined in a config.h header.
Makefile
ifeq ($(CONFIG_MY_DEFINE),y)
KBUILD_CFLAGS += -DTHE_REAL_DEAL=1 # THE_REAL_DEAL now '1' in C files.
endif
Source
#ifdef CONFIG_MY_DEFINE
#define THE_REAL_DEAL 1
#endif
So, the Kconfig section defines the user interface information. The .config is makefile syntax, which is output by menuconfig, etc. This is sourced when you type make. Ie, all the stuff selected by menuconfig or another tool is available in Makefiles. The Kconfig variable has a CONFIG_ prefix added.
You can choose either the Makefile or the Source sections to get your define. If you want to select a range, then you can pass the value of CONFIG_MY_DEFINE to the compiler. Ie, including almost any kernel header will include config.h and the 'C' value CONFIG_MY_DEFINE will be set to whatever the user selected in the range.
See the kbuild wiki for more, which mainly references the kernel's kbuild documentation.
Related
I want to compile my c code (in kernel) which needs to include some header files from another directory.
Instead of specifying the complete path to header files in c file, I would like to specify the include path in Makefile.
My c file gets complied when the config option CONFIG_FEATURE_X is enabled.
I have written the following in Makefile:
obj-$(CONFIG_FEATURE_X) += my_file.o
ccflags-$(CONFIG_FEATURE_X) += -I$(obj)/../../path
When the CONFIG_FEATURE_X is enabled (Y) in .config using make menuconfig, it works fine.
But when the CONFIG_FEATURE_X is enabled as module (m) in .config, this does not include the header files from the path specified and gives the file not found error.
How can I do this?
When the CONFIG_FEATURE_X is enabled (Y) in .config using make menuconfig, it works fine.
That's because
ccflags-$(CONFIG_FEATURE_X) += -I$(obj)/../../path
would evaluate to
ccflags-y += -I$(obj)/../../path
According to Documentation/kbuild/makefiles.txt:
--- 3.7 Compilation flags
ccflags-y, asflags-y and ldflags-y
These three flags apply only to the kbuild makefile in which they
are assigned. They are used for all the normal cc, as and ld
invocations happening during a recursive build.
Note: Flags with the same behaviour were previously named:
EXTRA_CFLAGS, EXTRA_AFLAGS and EXTRA_LDFLAGS.
They are still supported but their usage is deprecated.
ccflags-y specifies options for compiling with $(CC).
So you have defined a valid compilation flag for the built-in case.
But when the CONFIG_FEATURE_X is enabled as module (m) in .config, this does not include the header files from the path specified and gives the file not found error.
That's because
ccflags-$(CONFIG_FEATURE_X) += -I$(obj)/../../path
would evaluate to
ccflags-m += -I$(obj)/../../path
According to the current version of Documentation/kbuild/makefiles.txt, there is no such compilation flag as "ccflags-m".
So the path specification is never used for the loadable module.
How can I do this?
Instead of the ccflags-$() flag, you could try to use CFLAGS_$#, a per-file options for $(CC).
CFLAGS_$#, AFLAGS_$#
CFLAGS_$# and AFLAGS_$# only apply to commands in current
kbuild makefile.
$(CFLAGS_$#) specifies per-file options for $(CC). The $#
part has a literal value which specifies the file that it is for.
Example:
# drivers/scsi/Makefile
CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF
CFLAGS_gdth.o = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
-DGDTH_STATISTICS
These two lines specify compilation flags for aha152x.o and gdth.o.
$(AFLAGS_$#) is a similar feature for source files in assembly
languages.
Example:
# arch/arm/kernel/Makefile
AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
So in your Makefile:
CFLAGS_my_file.o = -I$(obj)/../../path
As noted by the #sawdust answer, it seems (according to documentation) that only ccflags-y variable is supported, not a ccflags-m one.
However, for make things work you may use a "trick":
ccflags-y += ${ccflags-m}
Complete code:
obj-$(CONFIG_FEATURE_X) += my_file.o
ccflags-$(CONFIG_FEATURE_X) += -I$(obj)/../../path
# After all, add content of 'ccflags-m' variable to 'ccflags-y' one.
ccflags-y += ${ccflags-m}
Apart from the standard directories used by make to locate files loaded by include directives, is there any way to specify additional include paths within the makefile itself? I'm aware of the -I command-line GNU make option but I would like to know if there's any make variable to specify the same.
I suggested using the .INCLUDE_DIRS variable, but as pointed out in the comment below, that variable is read-only.
The only other way I can think of is to have a top-level file invoke the real makefile, and have the top level one update MAKEFLAGS:
# Top level -- Call it GNUmakefile?
INCLUDE_DIRS := first second third
MAKEFLAGS += $(foreach dir,$(INCLUDE_DIRS),--include-dir=$(dir))
.DEFAULT all:;$(MAKE) -f Makefile $(MAKECMDGOALS)
Then the real Makefile is invoked with the three directories in .INCLUDE_DIRS.
U-boot being a bootloader targeted at different architecture and SoC's, there are several source files, and only some of them makes it to the final executable for a particular board. For example, in the arch/ directory, there is one directory per architecture. If the build is for an ARM architecture SoC, only some of the files in arch/arm/ will be compiled into the executable.
Which of the source files get compiled into the executable depends on the configuration of the build. This configuration is controlled by a file present in configs/ directory. In case of BeagleBone Black, this file is configs/am335x_boneblack_defconfig. This file defines several variables, which are used in Makefiles.
A part of the configs/am335x_defconfig is shown below:
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
CONFIG_DISTRO_DEFAULTS=y
The variables defined in these files are later referenced in other Makefiles. For example, the CONFIG_AM33XX variable defined above is referenced in /arch/arm/mach-omap2/am33xx/Makefile as shown below:
obj-$(CONFIG_AM33XX) += clock_am33xx.o
obj-$(CONFIG_TI814X) += clock_ti814x.o
obj-$(CONFIG_AM43XX) += clock_am43xx.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
obj-y += clock.o
endif
I guess while executing the command
$make am335x_boneblack_defconfig
the value of the variable CONFIG_AM33XX gets replaced in some transient copy of the Makefile, so that the content of the above makefile gets replaced by
obj-y += clock_am33xx.o
Figuring out which source files are included in the final executable just by searching for the config variables in all the Makefiles is a tedious task.
I need a way to create a list of source files which gets compiled for a particular config file automatically. Is there a way to do it?
Just do a clean build and search for all object files:
make mrproper
make foo_defconfig
make -j6
find . -name '*.o'
You probably want to exclude directories tools/ and scripts/.
I can use the following command to create a Linux kernel .config file based on a specified architecture default for a custom ARM-based board:
ARCH=arm make defconfig KBUILD_DEFCONFIG=var_som_mx6_android_defconfig
I thought that this command more or less copies ./arch/arm/configs/var_som_mx6_android_defconfig to ./.config. However the resulting .config file isn't exactly a copy:
$ diff --unified arch/arm/configs/var_som_mx6_android_defconfig .config
--- arch/arm/configs/var_som_mx6_android_defconfig 2017-01-20 12:10:51.891515984 -0800
+++ .config 2017-01-26 15:31:29.000000000 -0800
## -407,6 +407,7 ##
CONFIG_ARM_ERRATA_751472=y
CONFIG_ARM_ERRATA_794072=y
CONFIG_ARM_ERRATA_761320=y
+CONFIG_ARM_ERRATA_845369=y
# CONFIG_ARM_ERRATA_753970 is not set
CONFIG_ARM_ERRATA_754322=y
# CONFIG_ARM_ERRATA_754327 is not set
## -2683,7 +2684,6 ##
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
# CONFIG_CUSE is not set
-CONFIG_AUFS_FS=y
#
# Caches
## -2759,6 +2759,21 ##
# CONFIG_PSTORE is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
+CONFIG_AUFS_FS=y
+CONFIG_AUFS_BRANCH_MAX_127=y
+# CONFIG_AUFS_BRANCH_MAX_511 is not set
+# CONFIG_AUFS_BRANCH_MAX_1023 is not set
+# CONFIG_AUFS_BRANCH_MAX_32767 is not set
+CONFIG_AUFS_SBILIST=y
+# CONFIG_AUFS_HNOTIFY is not set
+# CONFIG_AUFS_RDU is not set
+# CONFIG_AUFS_PROC_MAP is not set
+# CONFIG_AUFS_SP_IATTR is not set
+# CONFIG_AUFS_SHWH is not set
+# CONFIG_AUFS_BR_RAMFS is not set
+# CONFIG_AUFS_BR_FUSE is not set
+CONFIG_AUFS_BDEV_LOOP=y
+# CONFIG_AUFS_DEBUG is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
I don't understand where the extra lines are coming from, and I have always found the internal workings of the kernel configuration, makefiles, and build scripts to be difficult to understand. Can anyone explain where those lines in the .config might be coming from?
Motivation
The .config file is not simply copied from your defconfig file. The motivation for storing defconfig in such a format is next: in defconfig we can specify only options with non-default values (i.e. options we changed for our board). This way we can keep it small and clear. Every new kernel version brings a bunch of new options, and this way we don't need to update our defconfig file each time the kernel releases. Also, it should be mentioned that kernel build system keeps very specific order of options in defconfig file, so it's better to avoid modifying it by hand. Instead you should use make savedefconfig rule.
Simplified explanation
When .config file is being generated, kernel build system goes through all Kconfig files (from all subdirs), checking all options in those Kconfig files:
if option is mentioned in defconfig, build system puts that option into .config with value chosen in defconfig
if option isn't mentioned in defconfig, build system puts that option into .config using its default value, specified in corresponding Kconfig
Check scripts/kconfig/Makefile and scripts/kconfig/conf.c files to see how it's actually done.
More precise and detailed explanation
From "Kbuild: the Linux Kernel Build System" by Javier Martinez:
Defining Configuration Symbols: Kconfig Files
Configuration symbols are defined in files known as Kconfig files. Each Kconfig file can describe an arbitrary number of symbols and can also include (source) other Kconfig files. Compilation targets that construct configuration menus of kernel compile options, such as make menuconfig, read these files to build the tree-like structure. Every directory in the kernel has one Kconfig that includes the Kconfig files of its subdirectories. On top of the kernel source code directory, there is a Kconfig file that is the root of the options tree. The menuconfig (scripts/kconfig/mconf), gconfig (scripts/kconfig/gconf) and other compile targets invoke programs that start at this root Kconfig and recursively read the Kconfig files located in each subdirectory to build their menus. Which subdirectory to visit also is defined in each Kconfig file and also depends on the config symbol values chosen by the user.
Storing Symbol Values: .config File
All config symbol values are saved in a special file called .config. Every time you want to change a kernel compile configuration, you execute a make target, such as menuconfig or xconfig. These read the Kconfig files to create the menus and update the config symbols' values using the values defined in the .config file. Additionally, these tools update the .config file with the new options you chose and also can generate one if it didn't exist before.
Because the .config file is plain text, you also can change it without needing any specialized tool. It is very convenient for saving and restoring previous kernel compilation configurations as well.
Useful commands
You can use simpler syntax for make defconfig, like:
$ make ARCH=arm your_board_defconfig
See the full list of available defconfigs with:
$ make ARCH=arm help | grep defconfig
If you need to do reverse action (i.e. create a neat small defconfig from extensive .config), you can use savedefconfig rule:
$ make ARCH=arm savedefconfig
Also, as 0andriy mentioned, you can use diffconfig script to see changes from one .config to another one:
$ scripts/diffconfig .config_old .config_new
It also generates include/generated/autoconf.h.
This header file is included by C source files. On the other hand, .config is for the Makefile system.
The build system generates two files, and keeps them consistent.
I am trying to compile c++ files using make. But, it is not using -std=c++11 flag by default. Whenever I need to compile a program which uses c++11 specific features, I have to explicitly compile it using g++.
So, I want to ask how can I have make automatically use the option -std=c++11 for all my c++ files on my system.
If I need to change some global makefile for g++ , what is the location of the makefile on Linux Mint 18 and what needs to be changed or added?
Or do I need to create a Makefile for myself?
EDIT 1: I am invoking make like make myfile
And there are only .cpp files and their binaries in the directory. I don't have any Makefile in the directory.
EDIT 2: Here, myfile is the name of the c++ file which I want to compile.
When I run make with the -d option, I get the following output (I can not paste all of the output as it is quite long and is exceeding the body size limit so, I am including the screenshots of the output).
Image 1
And this image(2) has some lines from the end.
Image 2
I intentionally made a change in the file "MagicalWord.cpp" so that make finds something to make!
There is no "global makefile" and there is no way to change the default flags for all invocations of make (unless you edit the source code to GNU make and compile it yourself, which is a bad idea in this situation).
In your makefile(s), add the line:
CXXFLAGS += -std=c++11
Assuming you're using the built-in rules for compiling things, or that you're using the standard variables with your own rules, that will do what you need.
If that doesn't work we'll need to see your makefile or at least the rules you use to build your C++ source files (things like the -d output aren't useful here--that would be interesting if files weren't being built, that you thought should be or similar).
Setting a system-wide language for all your C++ projects isn't necessarily a good idea. Instead, define a Makefile that specifies any compiler options you'd like:
CXXFLAGS := -std=c++11 $(CXXFLAGS)
The CXXFLAGS are then passed to your compiler when compiling a C++ program (assuming you're using the default GNU Make rules).
If the Makefile lives in your current working directory, you can now run make target in order to compile a target.cpp file into a target executable.
If the Makefile is in another directory, you must specify the path to it:
make -f path/to/your/Makefile target
If you want to add extra parameters just for one run, you can set an environment variable or a make variable on the command line:
# environment:
CXXFLAGS='-std=c++11' make target
# make variable:
make target CXXFLAGS='-std=c++11'
Any of these will cause the execution of g++ -std=c++11 target.cpp -o target or equivalent.
In theory you can edit your shell profile to export CXXFLAGS='-std=c++11' which will make that environment variable available to all programs you run. In practice, setting compiler options through environment variables tends to cause more problems than it solves.
Of all these solutions, just writing a normal Makefile is by far the easiest approach. That way, all of the build configuration is in one place and completely automated.