I've been trying to compile some language (CISC) that my professor created which is pseudo assembly. He wanted us to make a makefile and compile the file with .asm extension using gcc.
This is the makefile:
.SUFFIXES: .asm
all:schemeCompiler
schemeCompiler:target.o
gcc -g -m32 -Wall -o schemeCompiler target.o
target.o: target.asm
gcc -m32 -g -Wall -ansi -c -o target.o target.asm
.PHONY: clean
clean:
rm -f *.o schemeCompiler
And this is the error I get:
gcc -m32 -g -Wall -ansi -c -o target.o target.asm
gcc: warning: target.asm: linker input file unused because linking not done
gcc -g -m32 -Wall -o schemeCompiler target.o
gcc: error: target.o: No such file or directory
gcc: fatal error: no input files
compilation terminated.
I've put the makefile with the asm file in the same directory
Thanks !
***We've figured out the problem , we weren't running the make command right. Also the makefile wasn't right:
.SUFFIXES: .asm
all:schemeCompiler
schemeCompiler:$#
gcc -g -m32 -Wall -o schemeCompiler $#
%: %.asm
gcc -x c -o $# $<
.PHONY: clean
clean:
rm -f *.o schemeCompiler
Related
I want to add -std=c++11 to my makefile but I do not Where to add, here is my code:
hw07: test.o functions.o
g++ test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ -c test.cpp
functions.o: functions.cpp headerfile.h
g++ -c functions.cpp
clean:
rm *.o hw07
in the above code where should I add the stdc++11 code, please help me out about...
Instead of spelling out all of the rules and all of the commands, use variables and implicit rules to build your program:
CXXFLAGS = -std=c++11
hw07: test.o functions.o
test.o: test.cpp headerfile.h
functions.o: functions.cpp headerfile.h
clean:
rm *.o hw07
This will have make build the object files using $(CXXFLAGS) as the options to pass to the compiler. Then make will build the program hw07 using the files listed in its dependencies.
Other flags that are good to have when compiling the source files are -Wall and -Wextra. Those enable more warning messages from the compiler, that in almost all cases point out suspect things that could lead to problems.
You can just add -std=c++11 after each g++:
hw07: test.o functions.o
g++ -std=c+++11 test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ -std=c+++11 -c test.cpp
functions.o: functions.cpp headerfile.h
g++ -std=c+++11 -c functions.cpp
clean:
rm *.o hw07
Also you can use a variable:
CPP_FLAGS='-std=c++11'
hw07: test.o functions.o
g++ ${CPP_FLAGS} test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ ${CPP_FLAGS} -c test.cpp
functions.o: functions.cpp headerfile.h
g++ ${CPP_FLAGS} -c functions.cpp
clean:
rm *.o hw07
I am having issues getting my Makefile to compile a very simple main function, and I can't seem to find the issue. Here is my Makefile:
main: main.o Recursion.o
gcc -Wall -o main main.o Recursion.o
main.o: main.c Recursion.c
gcc -Wall -c main.c
Recursion.o: Recursion.c Recursion.h
gcc -Wall -c Recursion.c
clean:
rm main *.o
When I enter the make command in the UNIX terminal, this is the result I get:
-bash-4.2$ make
cc -c -o main.o main.c
cc -c -o Recursion.o Recursion.c
gcc -Wall -o main main.o Recursion.o
main.o: main.c Recursion.c
make: main.o:: Command not found
make: *** [Makefile:3: main] Error 127
-bash-4.2$
I cannot figure out what's wrong. It is generating the executable main, but I'm not sure what exactly the issue is on the command line. Any suggestions?
Makefiles are indentation-sensitive.
Try this:
main: main.o Recursion.o
gcc -Wall -o main main.o Recursion.o
main.o: main.c Recursion.c
gcc -Wall -c main.c
Recursion.o: Recursion.c Recursion.h
gcc -Wall -c Recursion.c
clean:
rm main *.o
This is the makefile:
all: main
main: main.o sum/sum.o sum/add/add.o utils/utils.o
gcc -Wall main.o sum/sum.o sum/add/add.o utils/utils.o -o main
main.o: main.c utils/utils.h sum/sum.h
gcc -Wall -c main.c
sum/sum.o: sum/sum.c sum/sum.h add/add.h
gcc -Wall -c sum/sum.c
sum/add/add.o: sum/add/add.c add.h
gcc -Wall -c sum/add/add.c
utils/utils.o: utils/utils.c
gcc -Wall -c utils/utils.c
clean:
rm -f main main.o sum/sum.o sum/add/add.o utils/utils.o *~
When I run make all in bash, I get errors like:
-make: *** No rule to make target `add.h', needed by `sum/sum.o'. Stop.
-make: *** No rule to make target `sum.c', needed by `sum/sum.o'. Stop.
And I have a directory where everything is:
.:
main.c main.o Makefile sum utils
./sum:
add sum.c sum.h
./sum/add:
add.c add.h
./utils:
utils.c utils.h
Where did I go wrong?
I have a simple Makefile,
.PHONY: clean
PROGRAMS=$(patsubst main%.cpp,example%,$(wildcard main*.cpp))
all: ${PROGRAMS}
GCCVERSION=$(shell gcc -dumpversion)
GLCFLAGS=$(shell pkg-config --cflags gl)
CPPFLAGS=-Wall -O2 ${GLCFLAGS}
ifeq "${GCCVERSION}" "4.5.2"
CXXFLAGS=-std=c++0x
else
CXXFLAGS=-std=c++11
endif
GLLIBS=$(shell pkg-config --libs gl)
LIBS=${GLLIBS} -lglut
example%: main%.o shaders.o fileutils.o
${CXX} $^ ${LIBS} -o $#
clean:
rm -f *.o ${PROGRAMS}
But when I executed it, it delete the *.o files as last command. I don't know why:
$ make
g++ -std=c++11 -Wall -O2 -I/usr/include/libdrm -c -o main01.o main01.cpp
g++ -std=c++11 -Wall -O2 -I/usr/include/libdrm -c -o shaders.o shaders.cpp
g++ -std=c++11 -Wall -O2 -I/usr/include/libdrm -c -o fileutils.o fileutils.cpp
g++ main01.o shaders.o fileutils.o -lGL -lglut -o example01
rm main01.o fileutils.o shaders.o
Is there anything wrong with my Makefile?
Intermediate files are deleted by design: see Chained Rules in GNU make manual.
Use .SECONDARY or .PRECIOUS targets to keep your precioussss temp files.
Just to clarify the previous response, you need to add a special rule like
.PRECIOUS: myfile.o
I am pretty new to Makefiles and i am trying to build an executable from 3 files, file1.c, file2.c, and file1.h into an executable called exFile. Here's what I got:
all: exFile
exFile: file1.o file2.o
gcc -Wall -g -m32 repeat.o show.o -o repeat
file1.o: file1.c file1.h
gcc -Wall -g -m32 -S file1.c -o file1.o
file2.o: file2.c
gcc -Wall -g -m32 -S file2.c -o file2.o
I've searched the web for makefiles in this format, but i came up empty handed so i was wondering if someone can help. When it tries to compile i get:
usr/bin/ld:file1.o:1: file format not recognized; treating as linker script
I've compiled programs using assembly files but I'm not to sure what to do with c files or the file1.h file. file1.c includes file1.h so i have to link them (I think?). Any suggestions or links to a reference would be appreciated
You have two problems with your gcc command-line. First, you're specifying the -S flag, which causes gcc to emit assembly code, rather than object code. Second, you're missing the -c flag, which tells gcc to compile the file to an object file, but not link it. If you just remove -S and change nothing else, you'll end up with an executable program named file1.o and another named file2.o, rather than two object files.
Besides those errors, you could simplify your makefile by the use of pattern rules. I suggest you try the following instead:
all: exFile
exFile: file1.o file2.o
gcc -Wall -g -m32 $^ -o $#
%.o: %.c
gcc -Wall -g -m32 -c $< -o $#
file1.o: file1.h
Or, as EmployedRussian points out, you can go with something even more minimal that leverages more of the built-in features of GNU make:
CC=gcc
CFLAGS=-Wall -g -m32
all: exFile
exFile: file1.o file2.o
$(LINK.c) $^ -o $#
file1.o: file1.h
The -S switch to gcc tells it to output assembler so this:
gcc -Wall -g -m32 -S file1.c -o file1.o
Is putting assembler into file1.o but you want, presumably, to compile file1.c into object code:
gcc -Wall -g -m32 file1.c -o file1.o
When the linker gets your file1.o it is confused because file1.o is assembler when the linker is expecting object code, hence your error.
So get rid of the -S switches for file1.o and file2.o.