I am implementing something in VHDL, and I don`t understand the errors that I get:
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicF is
port(A,B,C:in std_logic; Y:out std_logic);
end LogicF;
architecture STRUCTURAL of LogicF is
signal notA, notB, andSign:std_logic;
begin
inv1:inverter port map (i=>A,o=>notA);
inv2:inverter port map (i=>B,o=>notB);
si1:and2 port map (i1=>notA, i2=>notB, o=>andSign);
sau1:or2 port map (i1=>andSign, i2=>C, o=>Y);
end STRUCTURAL;
Error: (3,10): Cannot find referenced context element.
Error: (8,1): Cannot find referenced entity declaration "LogicF"
As Brian points out Line 3, Character 10 (3,10) is the first character of the word primitive in use.work.primitive.all;. It seems the package hasn't been in the working library.
%% ghdl -a LogicF.vhdl
LogicF.vhdl:3:10: primary unit "primitive" not found in library "work"
ghdl: compilation error
%%
The question about which tool comes from the second error at (8,1), the entity LogicF did not successfully analyze and wasn't placed in the working library.
IEEE Std 1076 (the LRM), Design units and their analysis, Order of analysis:
If any error is detected while attempting to analyze a design unit,
then the attempted analysis is rejected and has no effect whatsoever
on the current working library.
The second error comes from the entity LogicF not being present in a referenced library.
(The LRM) same section (11.4 -1993, 13.5 -2008):
The rules defining the order in which design units can be analyzed are
direct consequences of the visibility rules. In particular:
a. A primary unit whose name is referenced within a given design unit must be analyzed prior to the analysis of the given design unit.
b. A primary unit must be analyzed prior to the analysis of any corresponding secondary unit.
An entity is a primary unit (LogicF) an architecture (STRUCTURAL) is a secondary unit.
When I used ghdl to analyze your design 'file' it quit after the first error. In this case because the second design unit was a secondary unit, the first failing was sufficient to stop analysis from succeeding. If there were further unrelated design units their analysis could have continued should they have proven to be error free (and didn't depend on the package primitives).
What's missing from the error messages are explanations of any assumptions, which are typically found in the tool implementation's documentation.
To answer Brian's question in his comment the format of the error message is from Aldec, apparently the Aldec-HDL tool (Google is useful betimes).
His was a professional curiosity question, Brian is one of the ghdl developers. There is no requirement VHDL that an error requires you to not analyze further design units found in the same design file. It's an implementation detail, where now we know what Aldec does.
Aldec doesn't share documentation other than with customers which otherwise makes it hard to seek third party help. You see a lot of universities publish tutorials on using Aldec tools.
I found the error message in another third party forum where the vendor was identified.
Related
I am using an Artix 7 FPGA and writing my code in Xilinx ISE.
I already have the Verilog code for the project I am working on. Unfortunately, I am not able to understand this module- The full code is posted here.
My goal is to find out where these 6 states are defined in the FSM: Reset (000), Wait for password (010), Compare (100), Log in successful (110), Login failed (111), and Do operation (101) and change the encoding to 4 bits.
I don't understand how the FSM in the image is there in the code.
Is anyone generous enough to help, please? Can I get a description of what is being done here?
The posted code is not Verilog RTL (Register Transfer Level) source code. Rather, its a post synthesis Verilog netlist. It contains the vendors primitives, look up tables (LUTS, buffers, etc). There is no way to understand the correlation between the bubble diagram and a post synthesis netlist in code linked to, its machine generated by the FPGA build tool (ISE in this case).
To correlate the bubble diagram and code, locate the corresponding Verilog source code that was used to create the netlist.
You might be able to locate the source code like this:
If you are on Linux, cd to near where the code is located and run
find . -iname '*.*v' | xargs grep 'Compare'
Here is an example of what a Verilog RTL state machine would look like:
https://www.asic-world.com/tidbits/verilog_fsm.html
The state variables and related logic are represented as parameter names (Verilog) or enumerations (in SystemVerilog). The state names are searchable using a text editor.
With VHDL '93 introducing direct instantiation, when would you actually use a component now when your entity is in VHDL? The following are the only time when a component is required I can think of:
Component maps to non VHDL source (Verilog, netlist etc)
You don't have the source yet and need something to compile against (eg. colleague hasn't finished their code yet)
You are binding different entity/architecture pairs to specific components in specific entities via configs. (but who ever actually does this? maybe if you have a simulation arch and synth arch - but again - never seen it used in any meaningful way)
I am discounting people who say that "A component lets me see the port map in the same file" or "having a component library allows me to see everything". This is mostly an old-school approach that people have got into the habit of. In my eyes, maintaining the same code in two places makes no sense.
Are there any others I've missed?
Sorry for the late response to Can't compile VHDL package - Modelsim error: (vcom-1576) expecting END
In addition to the use case listed by the OP and in compliance with his criteria of not so useful cases, I'll add two more cases:
To write platform independent code, one needs to implement e.g. an Altera and a Xilinx specific solution. This code will reference vendor specific libraries like alter_mf or unisim. Both vendor specific implementations can be selected by a if ... generate-statement, or since VHDL-2008 by a case ... generate-statement.
But even with generate-statements, this solution needs to instantiate components, because instances of a direct entity instantiation are bound regardless of the fact that some instances will never appear in the elaborated model. (I consider this a bug in the language - but there was no time to investigate and fix it for VHDL-2018.) Because an entity is immediately bound, the tool tries to load the referenced vendor library and it's packages.
Let's assume you compile on Altera with Quartus, it will complain about an unknown unisim library and a unknown vcomponents package. The same happens on Xilinx with Vivado complaining about an unknown altera_mf library.
Thus, to cut-off the (direct) instantiation tree, a component instantiation is needed.
This technique is used by the PoC-Library. See for example the PoC.misc.sync.Bits implementation for a standard double-FF synchronizer with different attributes applied to an Altera, Xilinx or generic implementation.
In the Open Source VHDL Verification Methodology (OSVVM), components are used for two use cases:
In a toplevel DUT, IP cores are instantiated as components so they can be replaced by dummy implementations. Either as unbound components or as components loading a dummy architecture. This can speed up simulations, reduce possible error sources in testing, replace complex slow implementations like MGTs or memory controllers with simpler and faster implementations, ...
In OSVVM, the test control is implemented in a separate entity called TestController. This entity has several architectures to implement the different test cases applied to the same test hardness. The architectures are bound with a toplevel configuration per test case / architecture. Thus, running a "testbench" means elaborating and simulating one of these configurations.
What's the simplest way to syntax-check my VHDL in Vivado without running through a full synthesis?
Sometimes I code many inter-related modules at once, and would like to quickly find naming errors, missing semi-colons, port omissions, etc. The advice I've read is to run synthesis, but that takes longer than I need for just a syntax check. I've observed that syntax errors will usually cause synthesis to abort within the first minute or so, so my workaround is to run synthesis and abort it manually after about a minute.
In the Vivado Tcl Console window, the check_syntax command performs a fast syntax check, catches typos, missing semi-colons, etc.
Vivado offers an elaboration step before synthesis. This is the lightweight version of y synthesis by just reading all sources and creating a design model based on the language without optimizations and transformations.
A pure syntax check per file is not enough in many cases. You also want to know if certain identifiers exist and if types are matching. Therefore, an elaboration is needed.
(If you never have heard of that step: VHDL compiling has 2 steps: Analysis and Elaboration. Think of elaboration like of linking in ANSI C.)
I am working in a VHDL code with a lot of SIGNALs that I should be able to see in the simulation on ModelSim to debug my design.
My question is whether is it necessary to declare outputs on my top-level entity so I can wire them an have access to those internal SIGNALs or is there any other way to access them from ModelSim?
If you can evaluate your design model interactively
Can you use a waveform dump display to debug your design? You can typically view any node in your design hierarchy.
If you need algorithmic or programmatic access for verification
Is your Modelsim -2008 compliant? For validation purposes in a testbench or block that is not synthesized you can use external names.
See IEEE Std 1076-2008, 8.2 External names. You can access signals, variables and constants by providing a pathname. External names are also described in Peter Ashenden's and Jim Lewis's book VHDL 2008 Just the New Stuff, Chapter 2.
In Modelsim
There's the show command which can access signals, processes, constants, variables, and entities. See the Modelsim Reference Manual, Commands, show. Commands can be entered from the command line or in macro files.
I am a newbie to VHDL and can't figure out how to debug VHDL code.
Is there any software that could probably give me an insight to the internal signals of my VHDL entity as time passes or something like that?
Please help.
As the other posts have pointed out, you'll likely need a simulator like GHDL. However, to debug your simulation, there are a few different methodologies:
Classic print statements -- just mix in writeline(output,[...]) in your procedural code. See this hello world example. If you're just getting started, then adding print statements will be invaluable. For most of the simulation debug that I do ( and that is part of my job ), I do almost all of the debug based on print statements that we've built up in our design and testbench. It is only for the final debug, or for more difficult issues that I use the next debug method.
"Dumping" the simulation ( for GHDL see this page and this one ). This is a cycle by cycle trace of your design ( or a subset of your design). It's as if you hook up a logic analyzer to every single wire in your design. All the info you could ever want about your design, but at a very low level -- the signal level. To use this methodology:
Create a simulation "dump". The base format for such a dump is a Value Change Dump or VCD. Whichever simulator you use, you'll need to read the documentation on how to create a VCD. ( You can also search "dump" in your docs -- your simulator may use a different file format for its dumps.)
Once you create a simulation dump, you then load your dump into a wave-form viewer. If you're using the gEDA package, then you would use gtkwave to view the dump.
note If you want to use GHDL and gtkwave to debug your VHDL code, you can install them on ubuntu with command:
% sudo apt-get install geda ghdl
( assuming you have root access to the machine running ubuntu)
Xilinx offers free version of its design suite: http://www.xilinx.com/tools/webpack.htm. Webpack contains VHDL simulator, although last time I tried I've liked ModelSim's simulator better. It might have changed though.
Wepack is also different from ModelSim as it's not only simulator but full-fledged FPGA design suite.
ModelSim's disadvantage is its license -- as far as I'm concerned it's free for students only.
The others mentioned here are likely more appropriate based on cost and availability. However the best HDL/netlist debugger I've used by far is Verdi.
What you are looking for is an VHDL simulator. There are several alternatives to choose from:
Mentors Modelsim
Xilinx ISim
Aldec Riviera and ActiveHDL
Simili
The Simili software is available as a free version with limited performance.
Once you have the simulator installed you need to learn how to use it. Generally you will have to write a testbench in VHDL too, but some of the simulators will let you create the stimuli signals from a graphical user interface. You can find a large number of examples of VHDL-based testbenches on this page: VHDL Tutorials.
In the simulator you are able to visually inspect the state of your design in the waveform viewer and also be able to set breakpoints in your code to debug the design.
Use a simulation software like ModelSim. This kind of software is usually quite expensive. In general if with your vhdl synthethizer you'll get some lightweight variant of it or similar software which is enough for smaller things.
For small jobs which don't push the language spec all the way, GHDL works fine as a simulator IME. As you push things further (and you must, you can't debug any sizeable piece of code just in silicon) you may find you need to spend some money on something like Mentor's Modelsim/Questa or Aldec's ActiveHDL/Riviera.
first i created test bench to test my component, used isim to simulate this test bench, i inserted break points in the main code areas, used the step into button to step into code, or the run button to jump to next break point
same as i am used to do with any programming language
The professional way to “Debug” VHDL is to create a “testbench”. Like everything else VHDL it’s complicated. Here’s a “how to testbench” link: vhdl Testbenches
I am very lazy. I am also not professional. I prefer to do what is known as “forcing”. If you are using Xilinx, ModelSim, or Vivado, then you have the ability to toss your VHDL code into a “simulation”. There you can add signals to a waveform, select those signals (right click on them) and force their values to be ‘0’ or ‘1’. Then after “forcing” your input, run the simulation for a few nanoseconds and look at the output.