Assembly 8086: get and print 32bit filesize using 16bit registers - tasm

i need to print a filesize using function 23h http://www.ousob.com/ng/asm/ng4d85d.php but i dont understand how can i get value from (offset 21h) of the FCB, it should be 4byte value, so need to move it into pair of 16bit registers, e.g. BX and CX
this is my simple code:
mov dx,offset input
mov ah,23h
int 21h
then i need to print it, but i just know how to print one 16bit register and i dont know find some tutorial how to do this for 32bit value (2 registers) simply,
thanks

The FCB returns both the number of records (a 32-bit quantity at offset 21h of the FCB) and the size of each record (a 16-bit quantity at offset 0Eh of the FCB). You need to multiply those together to get an approximation of the file size. It's only an approximation because a partial block is counted as a whole block for this call.
So assuming that input is already declared as an FCB structure in memory in the Data Segment and that your file consists exclusively of records that 27 bytes long, your code might look like this.
mov dx,offset input ; point to FCB
mov si, dx ; copy pointer
add si,0Eh ; point to record size within FCB
mov [si],27 ; load record size = 27 bytes
mov ah,23h ; get file size
int 21h ; call the DOS interrupt
cmp al,0 ; was the call successful?
jnz error ; if not, handle the error
add si,13h ; advance pointer to point to FCB:21h
; now ds:si points to file size in records
See this derivation of the age-old "Ralf Brown's interrupt list" for a list of some of the many precautions regarding this interrupt.

Related

cmp instruction and negative numbers [duplicate]

This question already has answers here:
Difference between JA and JG in assembly
(2 answers)
Closed 10 months ago.
Here is a code to sort the given array in assembly language
.model small
.stack 100h
.data ;roll number 2435
data1 db 66h, 2, 045h, 4, 040h, 3, -025h, 5, -010h, 011h
swap db 0
.code
mov ax, #data
mov ds, ax
start:
mov swap, 0
mov bx, 0
loop1:
mov al, [bx+data1]
mov cl, [bx+data1+1]
cmp al, [bx+data1+1] ;here is the problem when compare 66h with -025h
jbe noswap
mov dl, [bx+data1+1]
mov [bx+data1+1],al
mov [bx+data1], dl
mov swap, 1
noswap:
add bx,1
cmp bx,9
jne loop1
cmp swap,1
je start
mov ah, 04ch
int 21h
it compares all elements of array to sort in ascending order, but when it compares 66h with -025h, it implies that 66h is smaller and -025h is bigger and does not swap, mov to no swap lable
i have debugged it and found that at backend -025h is being stored as DB. How can I properly sort the array with negative number
Use the signed condition code in the conditional branch: e.g. jle instead of the unsigned condition code jbe. See https://sandpile.org/x86/cc.htm . If you ask the processor to do unsigned condition then it will see -025h as 0xDB, which is 219, so larger than 66h/102.
The processor doesn't read data declarations, so it doesn't see the minus sign.  Since it never sees declarations, it doesn't matter to the processor if you put db -25h or db 219 or db 0xdb — these will all populate the data with the same bit pattern value.
In C, for example, we give types to the variables and then the compiler (using language rules) generates machine code that accesses the variable consistently, i.e. as the size it was declared, and also as to whether signed or unsigned.
In assembly language we don't have variable declarations with expressive type information.  So, we must do the job that compilers do: use the proper size and signed'ness in the machine code for every access to variables.

algorithm of addressing a triangle matrices memory using assembly

I was doing a project in ASM about pascal triangle using NASM
so in the project you need to calculate pascal triangle from line 0 to line 63
my first problem is where to store the results of calculation -> memory
second problem what type of storage I use in memory, to understand what I mean I have 3 way first declare a full matrices so will be like this way
memoryLabl: resd 63*64 ; 63 rows of 64 columns each
but the problem in this way that half of matrices is not used that make my program not efficient so let's go the second method is available
which is declare for every line a label for memory
for example :
line0: dd 1
line1: dd 1,1
line2: dd 1,2,1 ; with pre-filled data for example purposes
...
line63: resd 64 ; reserve space for 64 dword entries
this way of doing it is like do it by hand,
some other from the class try to use macro as you can see here
but i don't get it
so far so good
let's go to the last one that i have used
which is like the first one but i use a triangle matrices , how is that,
by declaring only the amount of memory that i need
so to store line 0 to line 63 line of pascal triangle, it's give me a triangle matrices because every new line I add a cell
I have allocate 2080 dword for the triangle matrices how is that ??
explain by 2080 dword:
okey we have line0 have 1 dword /* 1 number in first line */
line1 have 2 dword /* 2 numbers in second line */
line2 have 3 dword /* 3 numbers in third line */
...
line63 have 64 dword /* 64 numbers in final line*/
so in the end we have 2080 as the sum of them
I have give every number 1 dword
okey now we have create the memory to store results let's start calculation
first# in pascal triangle you have all the cells in row 0 have value 1
I will do it in pseudo code so you understand how I put one in all cells of row 0:
s=0
for(i=0;i<64;i++):
s = s+i
mov dword[x+s*4],1 /* x is addresses of triangle matrices */
second part in pascal triangle is to have the last row of each line equal to 1
I will use pseudo code to make it simple
s=0
for(i=2;i<64;i++):
s = s+i
mov dword[x+s*4],1
I start from i equal to 2 because i = 0 (i=1) is line0 (line1) and line0 (line1)is full because is hold only one (tow) value as I say in above explanation
so the tow pseudo code will make my rectangle look like in memory :
1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
...
1 1
now come the hard part is the calculation using this value in triangle to fill all the triangle cells
let's start with the idea here
let's take cell[line][row]
we have cell[2][1] = cell[1][0]+cell[1][1]
and cell[3][1]= cell[2][0]+cell[2][1]
cell[3][2]= cell[2][1]+cell[2][2]
in **general** we have
cell[line][row]= cell[line-1][row-1]+cell[line-1][row]
my problem I could not break this relation using ASM instruction because i have a
triangle matrices which weird to work with can any one help me to break it using a relation or very basic pseudo code or asm code ?
TL:DR: you just need to traverse the array sequentially, so you don't have to work out the indexing. See the 2nd section.
To random access index into a (lower) triangular matrix, row r starts after a triangle of size r-1. A triangle of size n has n*(n+1)/2 total elements, using Gauss's formula for the sum of numbers from 1 to n-1. So a triangle of size r-1 has (r-1)*r/2 elements. Indexing a column within a row is of course trivial, once we know the address of the start of a row.
Each DWORD element is 4 bytes wide, and we can take care of that scaling as part of the multiply, because lea lets us shift and add as well as put the result in a different register. We simplify n*(n-1)/2 elements * 4 bytes / elem to n*(n-1) * 2 bytes.
The above reasoning works for 1-based indexing, where row 1 has 1 element. We have to adjust for that if we want zero-based indexing by adding 1 to row indices before the calculation, so we want the size of a triangle
with r+1 - 1 rows, thus r*(r+1)/2 * 4 bytes. It helps to put the linear array index into a triangle to quickly double-check the formula
0
4 8
12 16 20
24 28 32 36
40 44 48 52 56
60 64 68 72 76 80
84 88 92 96 100 104 108
The 4th row, which we're calling "row 3", starts 24 bytes from the start of the whole array. That's (3+1)*(3+1-1) * 2 = (3+1)*3 * 2; yes the r*(r+1)/2 formula works.
;; given a row number in EDI, and column in ESI (zero-extended into RSI)
;; load triangle[row][col] into eax
lea ecx, [2*rdi + 2]
imul ecx, edi ; ecx = r*(r+1) * 2 bytes
mov eax, [triangle + rcx + rsi*4]
This assuming 32-bit absolute addressing is ok (32-bit absolute addresses no longer allowed in x86-64 Linux?). If not, use a RIP-relative LEA to get the triangle base address in a register, and add that to rsi*4. x86 addressing modes can only have 3 components when one of them is a constant. But that is the case here for your static triangle, so we can take full advantage by using a scaled index for the column, and base as our calculated row offset, and the actual array address as the displacement.
Calculating the triangle
The trick here is that you only need to loop over it sequentially; you don't need random access to a given row/column.
You read one row while writing the one below. When you get to the end of a row, the next element is the start of the next row. The source and destination pointers will get farther and farther from each other as you go down the rows, because the destination is always 1 whole row ahead. And you know the length of a row = row number, so you can actually use the row counter as the offset.
global _start
_start:
mov esi, triangle ; src = address of triangle[0,0]
lea rdi, [rsi+4] ; dst = address of triangle[1,0]
mov dword [rsi], 1 ; triangle[0,0] = 1 special case: there is no source
.pascal_row: ; do {
mov rcx, rdi ; RCX = one-past-end of src row = start of dst row
xor eax, eax ; EAX = triangle[row-1][col-1] = 0 for first iteration
;; RSI points to start of src row: triangle[row-1][0]
;; RDI points to start of dst row: triangle[row ][0]
.column:
mov edx, [rsi] ; tri[r-1, c] ; will load 1 on the first iteration
add eax, edx ; eax = tri[r-1, c-1] + tri[r-1, c]
mov [rdi], eax ; store to triangle[row, col]
add rdi, 4 ; ++dst
add rsi, 4 ; ++src
mov eax, edx ; becomes col-1 src value for next iteration
cmp rsi, rcx
jb .column ; }while(src < end_src)
;; RSI points to one-past-end of src row, i.e. start of next row = src for next iteration
;; RDI points to last element of dst row (because dst row is 1 element longer than src row)
mov dword [rdi], 1 ; [r,r] = 1 end of a row
add rdi, 4 ; this is where dst-src distance grows each iteration
cmp rdi, end_triangle
jb .pascal_row
;;; triangle is constructed. Set a breakpoint here to look at it with a debugger
xor edi,edi
mov eax, 231
syscall ; Linux sys_exit_group(0), 64-bit ABI
section .bss
; you could just as well use resd 64*65/2
; but put a label on each row for debugging convenience.
ALIGN 16
triangle:
%assign i 0
%rep 64
row %+ i: resd i + 1
%assign i i+1
%endrep
end_triangle:
I tested this and it works: correct values in memory, and it stops at the right place. But note that integer overflow happens before you get down to the last row. This would be avoided if you used 64-bit integers (simple change to register names and offsets, and don't forget resd to resq). 64 choose 32 is 1832624140942590534 = 2^60.66.
The %rep block to reserve space and label each row as row0, row1, etc. is from my answer to the question you linked about macros, much more sane than the other answer IMO.
You tagged this NASM, so that's what I used because I'm familiar with it. The syntax you used in your question was MASM (until the last edit). The main logic is the same in MASM, but remember that you need OFFSET triangle to get the address as an immediate, instead of loading from it.
I used x86-64 because 32-bit is obsolete, but I avoided too many registers, so you can easily port this to 32-bit if needed. Don't forget to save/restore call-preserved registers if you put this in a function instead of a stand-alone program.
Unrolling the inner loop could save some instructions copying registers around, as well as the loop overhead. This is a somewhat optimized implementation, but I mostly limited it to optimizations that make the code simpler as well as smaller / faster. (Except maybe for using pointer increments instead of indexing.) It took a while to make it this clean and simple. :P
Different ways of doing the array indexing would be faster on different CPUs. e.g. perhaps use an indexed addressing mode (relative to dst) for the loads in the inner loop, so only one pointer increment is needed. But if you want it to run fast, SSE2 or AVX2 vpaddd could be good. Shuffling with palignr might be useful, but probably also unaligned loads instead of some of the shuffling, especially with AVX2 or AVX512.
But anyway, this is my version; I'm not trying to write it the way you would, you need to write your own for your assignment. I'm writing for future readers who might learn something about what's efficient on x86. (See also the performance section in the x86 tag wiki.)
How I wrote that:
I started writing the code from the top, but quickly realized that off-by-one errors were going to be tricky, and I didn't want to just write it the stupid way with branches inside the loops for special cases.
What ended up helping was writing the comments for the pre and post conditions on the pointers for the inner loop. That made it clear I needed to enter the loop with eax=0, instead of with eax=1 and storing eax as the first operation inside the loop, or something like that.
Obviously each source value only needs to be read once, so I didn't want to write an inner loop that reads [rsi] and [rsi+4] or something. Besides, that would have made it harder to get the boundary condition right (where a non-existant value has to read as 0).
It took some time to decide whether I was going to have an actual counter in a register for row length or row number, before I ended up just using an end-pointer for the whole triangle. It wasn't obvious before I finished that using pure pointer increments / compares was going to save so many instructions (and registers when the upper bound is a build-time constant like end_triangle), but it worked out nicely.

How to find the physical address of interrupts in interrupt vector table?

How do i calculate the physical address of any given interrupt (INT22H or INT15H for instance) in the interrupt vector table for 8086 microprocessor?
...calculate the physical address of any given interrupt (INT22H or INT15H for instance) in the interrupt vector table...
Physical address where the int 15h instruction finds the far pointer that it should call.
This is an offset within the Interrupt Vector Table, and so gives a physical address aka linear address from the list {0,4,8,12, ... , 1016,1020}.
Since each vector is 4 bytes long, all it takes is multiplying the interrupt number by 4.
mov ax,0415h ;AL=Interrupt number, AH=4
mul ah ; -> Product in AX
cwd ;(*) -> Result in DX:AX=[0,1023]
(*) I like all my linear addresses expressed as DX:AX. That's why I used the seemingly unnecessary cwd instruction.
Physical address where int 15h ultimately gets handled.
This can be anywhere in the 1MB memory. (On 8086 there's no memory beyond 1MB).
Each 4 byte vector consists of an offset word followed by a segment word. The order is important.
The linear address is calculated from multiplying the segment value by 16 and adding the offset value.
mov ax,16
mul word ptr [0015h * 4 + 2] ;Segment in high word -> Product in DX:AX
add ax, [0015h * 4] ;Offset in low word
adc dx, 0 ; -> Result in DX:AX=[0,1048575]

what is fs:[register+value] meaning in assembly?

xor ebx,ebx
mov eax,DWORD PTR fs:[ebx+0x3]
I know first line of this code, but what's fs:[ebx+0x3]?
and why it giving me an error while compiling ?
test.asm:2: error: comma, colon, decorator or end of line expected after operand
The xor opcode sets EBX to 0. So the mov opcode accesses a DWORD at fs:[3]. This accesses the last byte of the Win32 Thread Information Block's Current Structured Exception Handling (SEH) frame located from fs:[0] to fs:[3] (4 bytes) and the first three bytes of the Stack Base variable, the initial value of ESP.
Unless you are confronted with some sophisticatedly constructed and obfuscated virus or anti-debugging-technique which combines these 3+1 bytes to something useful, this would just be a somewhat random number.
Another possibility is, that the "segment" register FS has been modified prior to these instructions to contain a sensible base address. In that case, this may be an useful instruction like many others. It is undecidable by the code snippet you provided.
For example
mov eax, fs
inc eax
mov fs, eax
...
xor ebx,ebx
mov eax,DWORD PTR fs:[ebx+0x3]
would return the 'Stack Base' in EAX - '(FS+1)+(0+3)' = real-FS:[4] = 'Stack Base' location.
Addition: For completeness: why it doesn't assemble has been mentioned in the comments by 'Ross Ridge': It's MASM syntax and not NASM syntax.

How can I write an interpreter for 'eq' for Hack Assembly language?

I am reading and studying The Elements of Computing Systems but I am stuck at one point. Sample chapter skip the next 5 instruction s can be found here.
Anyway, I am trying to implement a Virtual Machine (or a byte code to assembly translator) but I am stuck at skip the next 5 instruction one point.
You can find the assembly notation here.
The goal is to implement a translator that will translate a specific byte code to this assembly code.
An example I have done successfully is for the byte code
push constant 5
which is translated to:
#5
D=A
#256
M=D
As I said, the assembly language for Hack is found in the link I provided but basically:
#5 // Load constant 5 to Register A
D=A // Assign the value in Reg A to Reg D
#256// Load constant 256 to Register A
M=D // Store the value found in Register D to Memory Location[A]
Well this was pretty straight forward. By definition memory location 256 is the top of the stack. So
push constant 5
push constant 98
will be translated to:
#5
D=A
#256
M=D
#98
D=A
#257
M=D
which is all fine..
I also want to give one more example:
push constant 5
push constant 98
add
is translated to:
#5
D=A
#256
M=D
#98
D=A
#257
M=D
#257 // Here starts the translation for 'add' // Load top of stack to A
D=M // D = M[A]
#256 // Load top of stack to A
A=M // A = M[A]
D=D+A
#256
M=D
I think it is pretty clear.
However I have no idea how I can translate the byte code
eq
to Assembly. Definition for eq is as follows:
Three of the commands (eq, gt, lt) return Boolean values. The VM
represents true and false as 􏰁-1 (minus one, 0xFFFF) and 0 (zero,
0x0000), respectively.
So I need to pop two values to registers A and D respectively, which is quite easy. But how am I supposed to create an Assembly code that will check against the values and push 1 if the result is true or 0 if the result is false?
The assembly code supported for Hack Computer is as follows:
I can do something like:
push constant 5
push constant 6
sub
which will hold the value 0 if 2 values pushed to the stack are equal or !0 if not but how does that help? I tried using D&A or D&M but that did not help much either..
I can also introduce a conditional jump but how am I supposed to know what instruction to jump to? Hack Assembly code does not have something like "skip the next 5 instructions" or etc..
[edit by Spektre] target platform summary as I see it
16bit Von Neumann architecture (address is 15 bits with 16 bit Word access)
Data memory 32KW (Read/Write)
Instruction (Program) memory 32KW (Read only)
native 16 bit registers A,D
general purpose 16 bit registers R0-R15 mapped to Data memory at 0x0000 - 0x000F
these are most likely used also for: SP(R0),LCL(R1),ARG(R2),This(R3),That(R4)
Screen is mapped to Data memory at 0x4000-0x5FFF (512x256 B/W pixels 8KW)
Keyboard is mapped to Data memory at 0x6000 (ASCII code if last hit key?)
It appears there is another chapter which more definitively defines the Hack CPU. It says:
The Hack CPU consists of the ALU specified in chapter 2 and three
registers called data register (D), address register (A), and program
counter (PC). D and A are general-purpose 16-bit registers that can be
manipulated by arithmetic and logical instructions like A=D-1 , D=D|A
, and so on, following the Hack machine language specified in chapter
4. While the D-register is used solely to store data values, the contents of the A-register can be interpreted in three different ways,
depending on the instruction’s context: as a data value, as a RAM
address, or as a ROM address
So apparently "M" accesses are to RAM locations controlled by A. There's the indirect addressing I was missing. Now everything clicks.
With that confusion cleared up, now we can handle OP's question (a lot more easily).
Let's start with implementing subroutine calls with the stack.
; subroutine calling sequence
#returnaddress ; sets the A register
D=A
#subroutine
0 ; jmp
returnaddress:
...
subroutine: ; D contains return address
; all parameters must be passed in memory locations, e.g, R1-R15
; ***** subroutine entry code *****
#STK
AM=M+1 ; bump stack pointer; also set A to new SP value
M=D ; write the return address into the stack
; **** subroutine entry code end ***
<do subroutine work using any or all registers>
; **** subroutine exit code ****
#STK
AM=M-1 ; move stack pointer back
A=M ; fetch entry from stack
0; jmp ; jmp to return address
; **** subroutine exit code end ****
The "push constant" instruction can easily be translated to store into a dynamic location in the stack:
#<constant> ; sets A register
D=A ; save the constant someplace safe
#STK
AM=M+1 ; bump stack pointer; also set A to new SP value
M=D ; write the constant into the stack
If we wanted to make a subroutine to push constants:
pushR2: ; value to push in R2
#R15 ; save return address in R15
M=D ; we can't really use the stack,...
#R2 ; because we are pushing on it
D=M
#STK
AM=M+1 ; bump stack pointer; also set A to new SP value
M=D ; write the return address into the stack
#R15
A=M
0 ; jmp
And to call the "push constant" routine:
#<constant>
D=A
#R2
M=D
#returnaddress ; sets the A register
D=A
#pushR2
0 ; jmp
returnaddress:
To push a variable value X:
#X
D=M
#R2
M=D
#returnaddress ; sets the A register
D=A
#pushR2
0 ; jmp
returnaddress:
A subroutine to pop a value from the stack into the D register:
popD:
#R15 ; save return address in R15
M=D ; we can't really use the stack,...
#STK
AM=M-1 ; decrement stack pointer; also set A to new SP value
D=M ; fetch the popped value
#R15
A=M
0 ; jmp
Now, to do the "EQ" computation that was OP's original request:
EQ: ; compare values on top of stack, return boolean in D
#R15 ; save return address
M=D
#EQReturn1
D=A
#PopD
0; jmp
#EQReturn1:
#R2
M=D ; save first popped value
#EQReturn2
D=A
#PopD
0; jmp
#EQReturn2:
; here D has 2nd popped value, R2 has first
#R2
D=D-M
#EQDone
equal; jmp
#AddressOfXFFFF
D=M
EQDone: ; D contains 0 or FFFF here
#R15
A=M ; fetch return address
0; jmp
Putting it all together:
#5 ; push constant 5
D=A
#R2
M=D
#returnaddress1
D=A
#pushR2
0 ; jmp
returnaddress1:
#X ; now push X
D=M
#R2
M=D
#returnaddress2
D=A
#pushR2
0 ; jmp
returnaddress2:
#returnaddress3 ; pop and compare the values
D=A
#EQ
0 ; jmp
returnaddress3:
At this point, OP can generate code to push D onto the stack:
#R2 ; push D onto stack
M=D
#returnaddress4
D=A
#pushR2
0 ; jmp
returnaddress4:
or he can generate code to branch on the value of D:
#jmptarget
EQ ; jmp
As I wrote in last comment there is a branch less way so you need to compute the return value from operands directly
Lets take the easy operation like eq for now
if I get it right eq a,d is something like a=(a==d)
true is 0xFFFF and false is 0x0000
So this if a==d then a-d==0 this can be used directly
compute a=a-d
compute OR cascade of all bits of a
if the result is 0 return 0
if the result is 1 return 0xFFFF
this can be achieved by table or by 0-OR_Cascade(a)
the OR cascade
I do not see any bit shift operations in your description
so you need to use a+a instead of a<<1
and if shift right is needed then you need to implement divide by 2
So when I summarize this eq a,d could look like this:
a=a-d;
a=(a|(a>>1)|(a>>2)|...|(a>>15))&1
a=0-a;
you just need to encode this into your assembly
as you do not have division or shift directly supported may be this may be better
a=a-d;
a=(a|(a<<1)|(a<<2)|...|(a<<15))&0x8000
a=0-(a>>15);
the lower and greater comparison are much more complicated
you need to compute the carry flag of the substraction
or use sign of the result (MSB of result)
if you limit the operands to 15 bit then it is just the 15th bit
for full 16 bit operands you need to compute the 16th bit of result
for that you need to know quite a bit of logic circuits and ALU summation principles
or divide the values to 8 bit pairs and do 2x8 bit substraction cascade
so a=a-d will became:
sub al,dl
sbc ah,dh
and the carry/sign is in the 8th bit of result which is accessible

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