Hi I am trying to write a 'Hello World' kernel module.
I wrote the following C code:
Module514.c
#include<linux/module.h>
#include<linux/kernel.h>
#include<linux/init.h>
MODULE_LICENSE("GPL");
MODULE_AUTHOR("BMC")
MODULE_DESCRIPTION(" My module]")
static int __init module514(void){
printk(KERN_INFO"Hello World");
return 0;
}
static void __exit module514_cleanup(void){
printk(KERN_INFO"unloaded")
}
module_init(module514);
module_exit(module514_cleanup);
Then created the following Makefile
obj-m += Module514.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
But when I give make I get the following message.
make: Nothing to be done for `all'.
What am I doing wrong.
The problem here seems to have been caused by my Vim configuration. When I used TAB to indent the makefile spaces were getting inserted instead of TAB. Once I corrected this using a different editor all is going file.
PS: Also makefile need to be named with capital M = Makefile
Related
I was re-implementing a simple linux file system and got this error when I ran make:
No rule to make target 'arch/x86/entry/syscalls/syscall_32.tbl', needed by 'arch/x86/include/generated/uapi/asm/unistd_32.h'. Stop.
More specifically, the error was like this:
This is my Makefile:
ifneq (${KERNELRELEASE},)
obj-m += evanfs.o
else
KERNEL_SOURCE := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C ${KERNEL_SOURCE} SUBDIRS=$(shell pwd) modules
clean:
rm *.o *.ko
endif
I've seen many similar posts but the solutions provided did not work for me.
Plus, I was actually following instructions from link and it was using kernel 2.6, however, my kernel is 5.15.0-53-generic, so maybe it's a matter of version?
Please help me fix this, thanks in advance!
I've scoured on the Internet and found no solutions that work for me...
Im trying to make a simple hello module.
This is the c file:
#include <linux/module.h> // included for all kernel modules
#include <linux/kernel.h> // included for KERN_INFO
#include <linux/init.h> // included for __init and __exit macros
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Daniel");
MODULE_DESCRIPTION("A Simple Hello World module");
static int __init hello_init(void)
{
printk(KERN_INFO "Hello world!\n");
return 0; // Non-zero return means that the module couldn't be loaded.
}
static void __exit hello_cleanup(void)
{
printk(KERN_INFO "Cleaning up module.\n");
}
module_init(hello_init);
module_exit(hello_cleanup);
This is the makefile:
obj-m := hello.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
Ive placed them in ~/HelloModule
and when I run the make command there it gives me this error:
make -C /lib/modules/4.13.0-25-generic/build M=/home/dan/HelloModule modules
make[1]: Entering directory '/usr/src/linux-headers-4.13.0-25-generic'
scripts/Makefile.build:44: /home/dan/HelloModule/Makefile: No such file or directory
make[2]: *** No rule to make target '/home/dan/HelloModule/Makefile'. Stop.
Makefile:1550: recipe for target '_module_/home/dan/HelloModule' failed
make[1]: *** [_module_/home/dan/HelloModule] Error 2
make[1]: Leaving directory '/usr/src/linux-headers-4.13.0-25-generic'
makefile:4: recipe for target 'all' failed
make: *** [all] Error 2
For some reason on the 4th line it seems like the make script is trying to go into the directory /home/dan/HelloModule/Makefile, which isn't a directory. any ideas on why this is happening and how to fix it?
I figured it out. its not trying to access a directory its trying to access the Makefile which is case sensitive so it has to be Makefile not makefile
I am trying to learn kernel programming but while trying to compile a simple hello world program i am getting the following error.
make −C /lib/modules/3.2.0-67-generic/build M=/home/arun/KPrograms modules
make[1]: Entering directory /home/arun/KPrograms'
make[1]: *** No rule to make target−C'. Stop.
make[1]: Leaving directory `/home/arun/KPrograms'
make: * [all] Error 2
my Makefile is
obj−m += hello−1.o
all:
make −C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make −C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
You should replace all the −C in Makefile into -C. The dash character is incorrect.
Hi all,
You must type your code on your own. In some cases copy paste does not work. You must enter it like this:
obj-m............<enter>
all:....<enter>
<tab>make -C.............<enter>
clean:..............<enter>
<tab>make -C...........<esc> <:wq>
That will probably solve your problem.
good luck
I have simple module program which will call to other function which are in other files. eg:
Arith.c <=== main module which calls sum(), diff(), mul() ...
|
|----sum.c
|----Sub.c
|----mul.c
|----div.c
|----remainder.c
|----quotient.c
I wrote the program for it. For make file I didn't understand how to write. I studied section 3.3 here and edited Makefile.
So now my make file is (I tested only for sum)
obj-m := arith.o
arith-y += sum.o
KDIR=/lib/modules/$(shell uname -r)/build
module:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
clean:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) clean
When I run make it compiled and generated arith.ko. When I inserted it not showing anything in dmesg. When I inserted other modules dmesg working properly.
arith.c:
extern void sum(void);
int init_module(void)
{
pr_info("module inserted..\n");
sum();
return 0;
}
void cleanup_module(void)
{
pr_info("module removed..\n");
}
sum.c:
void sum(void)
{
pr_info("sum of 1 and 2: %d\n", 1+2);
}
Additional Info:
If I comment arith-y += sum.o in Makefile and not calling sum function in arith.c, dmesg working correctly.
Questions:
1.Is that make file correct?
2.If it is correct, why arith module not showing anything in dmesg even other modules working fine?
3.If it is not correct, how to write Makefile and why?
You never refer to obj-m or arith-y after declaring them; so they are either:
some sort of magic that your make knows about (which I doubt),
normal variables which you need to reference somewhere else, or
dead code.
You might have more luck looking through the kernel tree for a simple makefile which you can read and understand in detail.
I am a newbie in Kernel Development. I was trying to understand the following makefile for Hello World! program. But I am not able to figure it out completely.
obj-m += hello.o
all:
sudo make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
sudo make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
I am not able to understand what is meant by 'obj-m += hello.o' . I know m here means module and thats it.
Also why are we not defining the dependencies of hello.o
And lastly I am not able to figure out completely the compiling rules defined under all: and clean:
Any help would be highly appreciated.!!
obj-m is a Makefile variable. It actually consists of 2 parts: 'obj' means that the referred target is a kernel object, while 'm' part means that the object is to be build like a module.
The variable is considered by kernel build rules. As kernel modules follow a certain convention, running your Makefile will result in creation of module hello.ko from source file hello.c (if everything works properly).
The 'obj' variable may take different suffixes as well. For example 'obj-y' will try to link the referred object into the main kernel image, instead of creating a module. The suffix may also refer to a kernel .config file variable, like this:
obj-$(CONFIG_HOTPLUG) += hotplug.o
In this case, if CONFIG_HOTPLUG is set to 'y' the hoplug object will be compiled into the main kernel; if set to 'm' then a separate hotplug.ko loadable module will be created. If not set to anything (resulting in 'obj-'), hotplug will be omitted outright.