When I'm compiling something, it gives errors like this:
$ make
CC test/hello.o
test/hello.c:37:29: fatal error: this/is/hard/to/find.h: No such file or directory
Then, is it possible to see the full command of CC (with all the options) by just giving an proper option to make without modifying Makefile?
Usually when a Makefile is set up to print summary lines like this instead of the full command, they also define a VERBOSE or QUIET variable to control that behavior. You might try just running make as make VERBOSE=1, but if that doesn't work you'll have to check the Makefile to see if it supports verbose output through some other mechanism, or post some of your Makefile for us to see.
Alternatively, you could use something like ElectricAccelerator, a high-performance replacement for GNU make that, among other features, can produce an XML-marked-up version of your build log, including all the command-lines for every command invoked, even if the Makefile normally only prints summaries like you've shown.
(Disclaimer: I'm the architect and lead developer of ElectricAccelerator)
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I tried to use a make file in code::blocks but I am doing it wrong. I have the version installed with the compilers included. http://sourceforge.net/projects/codeblocks/files/Binaries/10.05/Windows/codeblocks-10.05mingw-setup.exe/download. What do I do with the make file? It starts with:
CC=gcc
best, US
You don't tend to execute the make file itself, rather you execute make, giving it the make file as an argument:
make -f pax.mk
If your make file is actually one of the standard names (like makefile or Makefile), you don't even need to specify it. It'll be picked up by default (if you have more than one of these standard names in your build directory, you better look up the make man page to see which takes precedence).
As paxdiablo said make -f pax.mk would execute the pax.mk makefile, if you directly execute it by typing ./pax.mk, then you would get syntax error.
Also you can just type make if your file name is makefile/Makefile.
Suppose you have two files named makefile and Makefile in the same directory then makefile is executed if make alone is given. You can even pass arguments to makefile.
Check out more about makefile at this Tutorial : Basic understanding of Makefile
There are many ways to produce a verbose make command with cmake.
This has been described in many places. (basically cmake; make VERBOSE=1 or set the CMAKE_VERBOSE_MAKEFILE variable).
Verbose here refers to showing the invoked commands and other information on the steps taken by make.
This seems to be an all or nothing setting.
Either you see all the commands or none of the commands,
regardless of the whether the command succeed or not.
A related tool, ctest (for testing) has a very useful options --output-on-failure for which verbosity depends on the particular test being successful;
only showing the screen out for failing tests.
The question is whether cmake has a similar feature regarding giving details only on failure.
That is, for the most part I don't want to see make compilation commands, but when it fails I would like to see what is the exact command that failed with all the options on display.
That is, the question is if there is some setting or command-line option for make or cmake that, in the build step, will print the full issued command (and output) only for commands that failed.
The reason of course is that it gives the opportunity to see the actual compilation flags for the failing step and allows to reproduce the exact command interactively sometimes.
(I use C++, but the question is general I think)
This is not exactly an answer because you only mentioned make, but what you ask is the default behavior of Ninja. It only outputs the command that failed.
Sometimes, when I am too desperate and I cannot understand the error messages I do this:
make -j 10 -k || make VERBOSE=1
So it will compile fast, and if it fails it runs again serially in verbose mode. It is very likely that the first compilation is the one failing.
I'm working on a project which requires using make.
From the command like I run either make Release or make Debug.
However, there is not a makefile in the directory in which I run the make command.
How can I tell which makefile the make command is using?
In GNU make you can use the make variable MAKEFILE_LIST to inspect which makefile(s) were read; yes, there can be more than one due to multiple -f options and include directives.
If you need the name of the last read makefile, use $(lastword $(MAKEFILE_LIST)).
See also the GNU make manual.
GNU make has a debug option. If you use -d, make will print all debugging output.
The debug level can be changed with --debug[=FLAGS].
--debug=v should show you which makefiles were parsed.
GNU make manual:
v (verbose):
A level above ‘basic’; includes messages about which makefiles were parsed, prerequisites that did not need to be rebuilt, etc. This option also enables ‘basic’ messages.
See the man page for additional information.
I'm building a Makefile for a sequence of compiles to show progressive output differences to be used to synchronize with the examples in a tutorial. Some of those runs generates error codes, but since that is part of the definition of the "problem" the message output by make ("Makefile:15: recipe for target `run3' failed") when a target fails kind of gets in the way.
I know about ignoring the error code, but is it possible to suppress that output? Preferable from within the Makefile.
On a similar note, is it possible to suppress the message of entering and leaving subdirectories from within the Makefile (equivalent to '--no-print-directory')?
And, yes, I'm satisfied with a GNU Make answer.
Of course, after some googling the answer is in the GNU Make manual. The special targets .SILENT and .IGNORE did exactly what I wanted.
To achieve what you want I would use --silent --ignore-errors --no-print-directory GNU make switches and redirect stderr to /dev/null (2>/dev/null) commands in the makefile
Currently, I'm using a Makefile to keep track of all dependencies and copilation of my project. The problem is that make simply outputs everything it's doing, and that makes it hard to spot (or even read) more important information (such as compiler warnings).
Is there a way to control what information is displayed on the terminal? I know there's a -s option that silences make, but that's not what I want. I need something a little more refined, perhaps showing the compilation target without showing the entire compilation command.
Is there any way to control that?
Note: There's a similar question regarding the automake and autoconf commands. But I don't use those, and I'm specifically looking for something on make.
Well there's the usual business
target: dependency1 dependency2
#echo Making $#
#$(CC) -o $# $(OPTIONS) $^
The leading #'s suppress the usual behavior of echoing the action without suppressing its output.
The output of various actions can be suppressed by redirecting it to /dev/null. Remember to grad the standard error too if you want a line to be really silent.
The standard Unix answer (`make`` is a Unix tool, after all):
make (...) | grep (whatever you want to see)
Why is that not an appropriate solution here?
You could also put filtering within the Makefile itself, e.g. by tweaking the SHELL variable
or adding a target that calls $(MAKE) | grep.
The main idea is to allow the filtering to be switched on and off as the caller pleases.
(Too late, Adding just for Googlers landing here)
This works for me. On your Makefile you can control verbosity for each command using something like:
BRIEF = CC HOSTCC HOSTLD AS YASM AR LD
SILENT = DEPCC DEPHOSTCC DEPAS DEPYASM RANLIB RM STRIP