Unexpected delays with register VHDL - vhdl

Question

Found a strange occurance with this register I coded. I'm very new to VHDL, but I was taught when writing a value to output ports like data_out you should always use a "middleman" signal to transfer your value. Here I tried to use the signal "data" to transfer the signal, but this implementation resulted in a delay before data_out changes (when ld goes high). Taking out data completely and coding how I would in a C program removes this delay and the register works perfectly. Any idea on why this is and why I shouldn't do this?
Broken code:
entity register is
generic (
DATA_WIDTH : natural := 12);
port (
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
ld : in std_logic;
clk : in std_logic;
rst_L : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity register;
architecture bhv of register is
signal data : std_logic_vector(DATA_WIDTH-1 downto 0);
begin -- bhv
REG : process (clk, rst_L, ld, data_in)
begin -- process REG
if rst_L = '0' then
data <= (others => '0');
else
if clk'event and clk = '1' then
if ld = '1' then
data <= data_in;
end if;
end if;
end if;
data_out <= data;
end process REG;
end architecture bhv;
Changes for process that made it work:
REG : process (clk, rst_L, ld, data_in)
begin -- process REG
if rst_L = '0' then
data <= (others => '0');
else
if clk'event and clk = '1' then
if ld = '1' then
data_out <= data_in;
end if;
end if;
end if;
end process REG;
Just wanted to know what I did wrong and why I even have to use a signal to transfer the value if the code works fine. Thanks!

Answer 1

The problem in the broken process code is that data signal is not updated for
read until after a delta delay, thus the data_out update by
data_out <= data assign is postponed until next execution of the process code, thereby giving a delay in simulation.
Note that the ld and data_in in the sensitivity list of the initial process are not required, since use of these are guarded by rising clk.
Update of the code can be:
reg : process (clk, rst_L)
begin -- process REG
if rst_L = '0' then
data <= (others => '0');
else
if clk'event and clk = '1' then -- May be written as rising_edge(clk) instead
if ld = '1' then
data <= data_in;
end if;
end if;
end if;
end process REG;
data_out <= data;
It may be useful to take a look at
VHDL's crown jewel for some information about processes and delta cycles in VHDL.
Note that register is a VHDL reserved word, so it can't be used as identifier
for the entity.

Answer 2

Unexpected delays with register VHDL
The problem with the original process is that data is not in the sensitivity list, delaying the assignment to data_out until the next time the process executes instead of the next simulation data cycle. The process will execute on any transaction of a signal in the sensitivity list - originally as you indicated ld.
Adding data to the sensitivity list of your original process:
REG : process (clk, rst_L, data)
begin -- process REG
if rst_L = '0' then
data <= (others => '0');
else
if clk'event and clk = '1' then
if ld = '1' then
data <= data_in;
end if;
end if;
end if;
data_out <= data;
end process REG;
Will allow the assignment to data_out to occur in a delta simulation cycle instead of waiting until a transition on a signal currently in the sensitivity list.
I removed the extraneous signals from the sensitivity list for the same reason Morten did in his answer. These were causing execution of the process at other times, but not when a transaction occurred on data.
And yes, as long as you don't have the data_out signal in an expression (e.g. on the right hand side of an assignment statement) in your architecture you don't need the intermediary variable data and your simulation will go a bit faster.
Your changed process is the most efficient implementation once the sensitivity list is pared down.
Simply adding data to the sensitivity list would have caused the original process to simulate correctly, feel free to try it.