VHDL nested case statement for some case options - vhdl

Question

I am new to VHDL and working with case statements, I have something like the following:
process(state)
begin
case state is
when stop =>
a <= input;
b <= output;
when move =>
a <= input_1;
b <= output_1;
end case;
end process;
where a,b,input, output,input_1 and output 1 are signals.
My issue is that I want to have a nested case in only one of the options:
for example:
process(state)
begin
case state is
when stop =>
a <= input;
b <= output;
when move =>
a <= if c='0' then input_1 else input_2;
b <= if c='0' then output_1 else output_2;
end case;
end process;
My question is can i do something like above where not all case options are nested but only some of them are or is there any other way in such situation , i tried using when else but got an error, saying that such syntax is not supported.
Any help is appreciated

Answer 1

I'm not quite sure what you're asking here:
can i do something like above where not all case options are nested but only some of them are or is there any other way in such situation
but is this what you are trying to do? (Note that I've added c to the sensitivity list):
process(state,c)
begin
case state is
when stop =>
a <= input;
b <= output;
when move =>
case c is
when '0' =>
a <= input_1;
b <= output_1;
when '1' =>
a <= input_2;
b <= output_2;
when others => null;
end case;
end process;

Answer 2

Your question is fraught with perils. Assigning an output to an internal signal can require an output port mode of inout or buffer or VHDL 2008 support which isn't universal for synthesis. Generally mode buffer isn't supported either.
To get to the heart of your question sequential signal assignments supporting when else are supported in VHDL 2008 but not generally in synthesis.
A case statement choice contains sequential statements.
You can use an if statement instead:
library ieee;
use ieee.std_logic_1164.all;
entity foo is
port (
signal input: in std_logic;
signal output: inout std_logic;
signal input_1: in std_logic;
signal input_2: in std_logic;
signal output_1: inout std_logic;
signal output_2: inout std_logic
);
end entity;
architecture fum of foo is
signal a, b: std_logic;
signal c: std_logic;
type some_state is (stop, move);
signal state: some_state;
begin
UNLABELED:
process(state)
begin
case state is
when stop =>
a <= input;
b <= output;
when move =>
if c = '0' then
a <= input_1;
b <= output_1;
else
a <= input_2;
b <= output_2;
end if;
end case;
end process;
end architecture;
Notice your two evaluations of c have been collapsed into one.
Besides the conditional signal assignment states that are supported as sequential statements in VHDL 2008, there's also selected signal assignment statements (likewise generally not supported by synthesis as sequential statements).

Answer 3

VHDL before 2008 does not have a ternary operator (C-like ? :) for sequential
statements, so you can't write if c='0' then input_1 else input_2, but in
VHDL-2008 you can write input_1 when c='0' else input_2.
However, the compact coding style can be achieved by making a small function:
function ternary(cond : boolean; res_true, res_false : std_logic) return std_logic is
begin
if cond then
return res_true;
else
return res_false;
end if;
end function;
Whereby the move part of the code can be written like:
when move =>
a <= ternary(c='0', input_1, input_2);
b <= ternary(c='0', output_1, output_2);
You can also make a nested case like:
when move =>
case c is
when '0' =>
a <= input_1;
b <= output_1;
when others =>
a <= input_2;
b <= output_2;
end case;
Or do it with if then else as David showed.