I have implemented an OR gate with generic parameters, but I am currently having some issues implementing it with a for-generate.
entity OR_gate is
generic( n : natural := 2);
port(x : in std_logic_vector(1 to n);
z : out std_logic);
end OR_gate;
architecture Behavioral of OR_gate is
begin
process(x)
variable temp : std_logic;
begin
temp := '0';
G1: for i in 1 to N loop
temp := temp or x(i);
end generate G1;
z <= temp;
end process;
end Behavioral;
I have the G1 parameter which indicates a loop, however as far as that goes, I am lost.
It is not a generate (concurrent) loop when made inside a process. In this case it is just a regular loop, with syntax without the generate, thus as:
process(x)
variable temp : std_logic;
begin
temp := '0';
G1 : for i in 1 to N loop
temp := temp or x(i);
end loop G1;
z <= temp;
end process;
An alternative to the process, is to create a function, and then make a concurrent function call in order to generate z, like:
architecture Behavioral of OR_gate is
function or_reduct(slv : in std_logic_vector) return std_logic is
variable res_v : std_logic;
begin
res_v := '0';
for i in slv'range loop
res_v := res_v or slv(i);
end loop;
return res_v;
end function;
begin
z <= or_reduct(x);
end Behavioral;
Finally, if the tools support the logical reduction operators defined VHDL-2008, then you can simplify it all to:
z <= or x;
Related
Is it possible to create an alias variable/signal to improve readability of for loops in VHDL processes?
For instance, consider the following module which contains a process with inner for loops (code is for example purpose, I haven't test it):
library ieee;
use ieee.std_logic_1164.all;
entity MyModule is
port (
clk : in std_logic;
inData : in std_logic_vector(7 downto 0);
outData : out std_logic_vector(7 downto 0));
end MyModule;
architecture functional of MyModule is
type sample_vector is array (natural range <>) of std_logic_vector(9 downto 0);
type data_t is record
samples : sample_vector(3 downto 0);
-- other elements...
end record data_t;
type data_vector is array (natural range <>) of data_t;
signal data : data_vector(1 downto 0);
begin -- functional
process (clk)
begin -- process
if clk'event and clk = '1' then
-- Set outData(N) to '1' if at least 1 of the last 10 values of inData(N) was '1'
for d in data'RANGE loop
for s in data(0).samples'RANGE loop
data(d).samples(s)(9 downto 1) <= data(d).samples(s)(8 downto 0);
data(d).samples(s)(0) <= inData(d * 4 + s);
outData(d * 4 + s) <= '0';
for b in data(d).samples(s)'RANGE loop
if data(d).samples(s)(b) = '1' then
outData(d * 4 + s) <= '1';
end if;
end loop;
end loop;
end loop;
end if;
end process;
end functional;
Having to use data(d).samples(s) every time I need to reference that signal is cumbersome, so I'd rather use an alias-like variable, something like that instead (inspired from generate syntax, idx part is just a bonus):
-- Set outData(N) to '1' if at least 1 of the last 10 values of inData(N) was '1'
for d in data'RANGE loop
for s in data(0).samples'RANGE loop
alias sample : std_logic_vector(9 downto 0) is data(d).samples(s);
constant idx : integer := d * 4 + s;
begin
sample(9 downto 1) <= sample(8 downto 0);
sample(0) <= inData(idx);
outData(idx) <= '0';
for b in sample'RANGE loop
if sample(b) = '1' then
outData(idx) <= '1';
end if;
end loop;
end loop;
end loop;
Of course, this does not work. So, is there any way to achieve something like that in VHDL, or do we always have to specify the full signal "path" each time?
I could replace the loop body with a procedure, but having to declare the procedure code in a (far away) different place of the file reduces readability even more. I could also use a for ... generate construct, but this will create 1 process for each iteration and prevent me from using common process variables inside the iteration.
As indicated in question comments, this can be achieve using process variables:
process (clk)
variable sample : std_logic_vector(9 downto 0);
variable idx : integer;
begin -- process
if clk'event and clk = '1' then
-- Set outData(N) to '1' if at least 1 of the last 10 values of inData(N) was '1'
for d in data'RANGE loop
for s in data(0).samples'RANGE loop
-- Helpers
sample := data(d).samples(s);
idx := d * 4 + s;
outData(idx) <= '0';
for b in sample'RANGE loop
if sample(b) = '1' then
outData(idx) <= '1';
end if;
end loop;
sample(9 downto 1) <= sample(8 downto 0);
sample(0) <= inData(idx);
-- Do not forget to apply changes
data(d).samples(s) <= sample;
end loop;
end loop;
end if;
end process;
Of course, using process variables implies changing the operations order to get the same behavior.
Since process variables are read and written in the loops, I was worried the synthesis tools would believe the result of iteration N was dependent on the result of iteration N-1, and make implements the iterations in series (instead of in parallel). However, after unrolling the loop (which is what synthesis tools do), it gets clear the synthesis tools will see sample and idx values are not re-used between iterations.
I am implementing the following module:
library ieee;
use ieee.std_logic_1164.all;
entity Grant_Logic is
generic (
N : positive := 4
);
Port (
Priority_Logic0 : in std_logic_vector(N-1 downto 0);
Priority_Logic1 : in std_logic_vector(N-1 downto 0);
Priority_Logic2 : in std_logic_vector(N-1 downto 0);
Priority_Logic3 : in std_logic_vector(N-1 downto 0);
Gnt : out std_logic_vector (N-1 downto 0)
);
end Grant_Logic;
architecture Behavioral of Grant_Logic is
begin
gnt(0) <= Priority_Logic0(0) or Priority_Logic1(3) or Priority_Logic2(2) or Priority_Logic3(1);
gnt(1) <= Priority_Logic0(1) or Priority_Logic1(0) or Priority_Logic2(3) or Priority_Logic3(2);
gnt(2) <= Priority_Logic0(2) or Priority_Logic1(1) or Priority_Logic2(0) or Priority_Logic3(3);
gnt(3) <= Priority_Logic0(3) or Priority_Logic1(2) or Priority_Logic2(1) or Priority_Logic3(0);
end Behavioral;
I want to take advantage of for ... generate to implement the same circuit when N changes. I am using Xilinx so Vivado (vhdl'93) does not support custom types for ports in the IP generation.
However, for the architecture I would like to use for ... generate. The issue is that some logic is needed to generate each bit of gnt. What I have so far is:
gen_gnt_vertical: for y in 0 to N-1 generate
constant val, index : integer := 0;
begin
s_result <= '0';
gen_gnt_horizontal: for x in 0 to N-1 generate
begin
LOGIC BASED ON val, x and y to obtain the index
s_result <= s_result or s_Priority_Logic(x)(index);
end generate;
gnt(y) <= s_result;
end generate;
The logic to compute index is:
if(x>0)
{
val = y - x;
if (val < 0)
{
index = N + val;
}
else
index = val;
}
else
{
index = y;
}
I have a script that generates a vhdl file based on N but I would like to do it directly on vhdl. Is that possible?
Thanks for the help
EDIT: As #Tricky replied, a function did the trick. So, I have the following:
function index( N, x,y : natural) return natural is
variable val : integer;
variable index : integer := 0;
begin
if(x>0) then
val := y - x;
if(val < 0) then
index := N + val;
else
index := val;
end if;
else
index := y;
end if;
return index;
end function;
And the architecture:
architecture Behavioral of Grant_Logic is
signal s_Priority_Logic : t_Priority_logic;
signal s_result : std_logic_vector(N-1 downto 0) := (others=>'0');
begin
s_Priority_Logic(0) <= Priority_Logic0;
s_Priority_Logic(1) <= Priority_Logic1;
s_Priority_Logic(2) <= Priority_Logic2;
s_Priority_Logic(3) <= Priority_Logic3;
process(s_Priority_Logic)
variable result : std_logic;
begin
for y in 0 to N-1 loop
result := '0';
for x in 0 to N-1 loop
result := result or s_Priority_logic(x)(index(N, x, y));
end loop;
gnt_g(y) <= result;
end loop;
end process;
end Behavioral;
#Tricky using a function was the correct thing to get the index value. Alo for generate was not correct but for loop. I edited my question to show the final result
I'm learning VHDL language right now and I have some problems of understanding a part of the code in my course. I don't understand in process freq_counter this statement -> if(pwm_count < max_pwm_count), because we don't know the value of max_pwm_count and also I don't see any incrementation of variable pwm_count.
Thank you, guys!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity PWM is
generic (
freq : integer := 50; --50Hz
INPUT_CLK : integer := 50000000; --50MHz
BITH_DEPTH : integer := 8
);
Port (
ENABLE : in std_logic;
CLK : in std_logic;
PWM_OUT : out std_logic;
DUTY_CYCLE : in std_logic_vector(BITH_DEPTH-1 downto 0)
);
end PWM;
architecture behavioral of PWM is
constant max_freq_count : integer:= INPUT_CLK/freq;
constant pwm_step : integer := max_freq_count/2**BITH_DEPTH;
signal PWM_value : std_logic := '0';
signal freq_count : integer range from 0 to max_freq_count := 0;
signal pwm_count : integer range from 0 to 2**BITH_DEPTH := 0;
signal max_pwm_count : integer range from 0 to 2**BITH_DEPTH := 0;
signal pwm_step_count : integer range from 0 to max_freq_count := 0;
begin
max_pwm_count <= TO_INTEGER(unsigned(DUTY_CYCLE));
PWM_OUT <= PWM_value;
freq_counter: process(CLK)
begin
if rising_edge(CLK) then
if(ENABLE='0') then
if(freq_count < max_freq_count) then
freq_count <= freq_count + 1;
if(pwm_count < max_pwm_count) then
PWM_value<='1';
if(pwm_step_count<pwm_step) then
pwm_step_count<=pwm_step_count+1;
else
pwm_step_count<=0;
pwm_count<=0;
end if;
else
pwm_value<='0';
end if;
else
freq_count <= 0;
pwm_count <= 0;
end if;
else
PWM_value <= '0';
end if;
end if;
end process freq_counter;
end PWM;
We DO know the value of max_pwm_count : it is initialised to 0 and never re-assigned. Therefore the IF can never be true and ... so on.
As far as incrementing PWM_Count is concerned, your understanding seems to be better than the author's, which puts you in a reasonable position for the necessary re-write.
I recommend first writing a testbench so you can observe its behaviour, and get it correct in simulation.
I have a priority encoding function that returns a vector containing a 1 at the position where the first 1 is found in the input vector. The function works as expected, unless I try to negate the input vector. Here's an example that demonstrates the unexpected behavior:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity tb IS
end tb;
architecture run of tb is
constant N : natural := 5;
function get_first_one_in_vec (vec_in: std_logic_vector) return std_logic_vector is
variable ret: std_logic_vector(vec_in'high downto vec_in'low);
begin
ret := (others => '0');
for i in vec_in'low to vec_in'high loop
if vec_in(i)='1' then
ret(i) := '1';
exit;
end if;
end loop;
return ret;
end get_first_one_in_vec;
signal a : std_logic_vector(N-1 downto 0);
signal abar : std_logic_vector(N-1 downto 0);
signal first_a : std_logic_vector(N-1 downto 0);
signal first_nota : std_logic_vector(N-1 downto 0);
signal first_abar : std_logic_vector(N-1 downto 0);
begin
process
begin
a <= "10100";
wait for 10 ns;
a <= "01011";
wait for 10 ns;
wait;
end process;
abar <= not(a);
first_a <= get_first_one_in_vec(a);
first_nota <= get_first_one_in_vec(not(a));
first_abar <= get_first_one_in_vec(abar);
end run;
To my understanding, first_nota should be the same as first_abar. However, my simulator (ModelSim - Intel FPGA Starter Edition 10.5b, rev. 2016.10) thinks otherwise, as you can see here:
What am I missing here?
This works OK:
function get_first_one_in_vec (vec_in: std_logic_vector) return std_logic_vector is
variable ret: std_logic_vector(vec_in'length downto 1);
variable inp: std_logic_vector(vec_in'length downto 1) := vec_in;
begin
ret := (others => '0');
for i in inp'right to inp'left loop
if inp(i)='1' then
ret(i) := '1';
exit;
end if;
end loop;
return ret;
end get_first_one_in_vec;
https://www.edaplayground.com/x/3zP_
Why does yours not work? Well, when you call your function with the not operator* as part of the expression:
first_nota <= get_first_one_in_vec(not a);
the numbering of the input to the function is changed to 1 to by the not operator. Why? Here is the code for the not operator and you can see why:
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
-- pragma built_in SYN_NOT
-- pragma subpgm_id 204
--synopsys synthesis_off
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
--synopsys synthesis_on
BEGIN
--synopsys synthesis_off
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
--synopsys synthesis_on
END;
---------------------------------------------------------------------
Anyway, this breaks your code (which starts scanning from the other end of the word).
One way of making function agnostic to the ordering of the numbering of its input is to normalise the inputs like this:
variable inp: std_logic_vector(vec_in'length downto 1) := vec_in;
Once you have done this, you're in control. So, instead of loops from 'high downto 'low, we can be more explicit and loop from 'right to 'left:
for i in inp'right to inp'left loop
not is an operator not a function. You don't need the brackets.
when S3 =>
NS<=S5;
Rd_ack<='0';
if (u=0) then
send:=u;
NS<=S4;
end if;
if (v=0) then
send:=u;
NS<=S4;
end if;
when S4 =>
How can I compare u and v with 0 and u with v ?
I want following statements
if( v= u) then. ....
if( u= 0) then
u and v are signa
signal u, v: std_logic_vector(0 to 31);
In VHDL can i use send to store the value? send is a variable.
If when we go to state s4 we want to take data in send and assign it to a signal.
You've handicapped someone answering without providing type information for the numerical literal.
If you're serious about testing a std_logic_vector against an integer type you can write an equality operator ("=") function that performs the comparison:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fum is
end entity;
architecture foo of fum is
signal u,v: std_logic_vector (31 downto 0);
signal NS,S4: std_logic;
function "=" (a:std_logic_vector; b: natural) return BOOLEAN is
variable as_slv: std_logic_vector(a'range);
begin
as_slv := std_logic_vector(to_unsigned(b,as_slv'length));
for i in a'range loop
if a(i) /= as_slv(i) then
return FALSE;
end if;
end loop;
return TRUE;
end function;
begin
SOME_PROCESS:
process(u,v,S4)
variable send: std_logic_vector (u'range);
begin
if u = 0 then
send := u;
NS <= S4;
end if;
if v = 0 then
send := u;
NS <= S4;
end if;
end process;
end architecture;
This example code analyzes, elaborates and simulates (despite doing nothing interesting).
Notice this one uses natural as the type, std_logic_vector is inherently unsigned, it's a 'bag of bits'.
If you're instead interested in only testing for all '0' values:
architecture fee of fum is
signal u,v: std_logic_vector (31 downto 0);
signal NS,S4: std_logic;
constant ZERO: std_logic_vector (u'range) := (others => '0');
begin
SOME_PROCESS:
process(u,v,S4)
variable send: std_logic_vector (u'range);
begin
if u = ZERO then
send := u;
NS <= S4;
end if;
if v = ZERO then
send := u;
NS <= S4;
end if;
end process;
end architecture;
fum with architecture fee also analyzes, elaborates and simulates while doing nothing interesting.
The constant ZERO instead of the equivalent X"00000000", (others => '0') not allowed in the expression.
The scope of the variable send in this example code is limited to the declarative region, in this case to the process statement SOME_PROCESS. Assuming one were to flesh out the process with a case statement operating off a state value, send could be used to assign a signal in that process.
And instead of writing a new operator "=" function when comparing a numerical literal you could use type conversion:
architecture fie of fum is
signal u,v: std_logic_vector (31 downto 0);
signal NS,S4: std_logic;
begin
SOME_PROCESS:
process(u,v,S4)
variable send: std_logic_vector (u'range);
begin
if unsigned (u) = 0 then
send := u;
NS <= S4;
end if;
if unsigned(v) = 0 then
send := u;
NS <= S4;
end if;
v <= send;
end process;
end architecture;
This has a drawback when simulating:
#> ghdl -r fum
../../../src/ieee/numeric_std-body.v93:1710:7:#0ms:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../../src/ieee/numeric_std-body.v93:1710:7:#0ms:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
#>
comparison in the numerical domain (using package numeric_std's "=") is sensitive to metavalues.