Booth's algorithm Verilog synthesizable - algorithm

Question

I am trying to implement Booth's algorithm (a finite state machine implementation) for a Xilinx FPGA.
Basically, at the start signal I will initialize my auxiliary regs, then I will go in state 0, where I will start to compare the 2 bits and do the shifting. I will repeat this until state 4 is reached.
assign Result = P[8:1];
always#(posedge clk or negedge start)
if(start == 1)
begin
// initialize with start values
state <= 3'd0;
end
else
if(state == 3'd0 || state == 3'd1 || state == 3'd2 || state == 3'd3)
begin
// compare bits and shift data
end
endmodule
Test module
clk = 0;
a = 4'b0011;
b = 4'b0011;
b = ~b+1;
start = 1;
#10;
start = 0;
clk becomes ~clk after #5 time units.
I do not own an FPGA, so I cannot test the program (I'll have to test it later at class).
I am testing it with Icarus. The problem is that the auxiliary regs are not initialized before the first posedge of the clock.
What can I do in order to properly initialize my auxiliary variables and to maintain the code to be synthesizable? I've tried using a for loop and an initial begin, and the simulation works fine, but it will not work on the FPGA (because I have to use #delays).

Answer 1

For ASIC it is best to use active low resets to set initial values however for FPGAs it is common just to set initial values in an initial blocks.
initial begin
state = 'd0 ;
end
always#(posedge clk) begin
if(state == 3'd0 || state == 3'd1 || state == 3'd2 || state == 3'd3)begin
// compare bits and shift data
state <= 3'd4 ;
end
endmodule
Using active low resets.
always#(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= 'd0 ;
end
else begin
if(state == 3'd0 || state == 3'd1 || state == 3'd2 || state == 3'd3)begin
// compare bits and shift data
state <= 3'd4 ;
end
end
endmodule