No sure if anyone knows the answer of this question, I looked around and can’t find a solution yet. I have a makefile that looks like the following:
MODELS := abc def
all: all_models
all_models: $(foreach m,$(MODELS),test$(m))
test%:
echo $(subst test,,$#)
Output:
echo abc
abc
echo def
def
I know the $(m) abc and def are passed in via test%: My question is what if for some file dependency reason, I have to hardcode test%: to something like “test:” how do I retrieve the arguments, i.e abc and def? For example the new clause is like
test:
# how do I retrieve abc and def from MODELS ?
Thank
I still don't think you're asking for what you really want, but here goes.
In the file models:
MODELS := abc def ghi jkl
In the makefile:
include models
test:
#echo do something with $(word 1,$(MODELS))
#echo MODELS := $(wordlist 2,$(words $(MODELS)), $(MODELS)) > models
Related
I have the following:
FILE_1_DEPS := a b c
FILE_2_DEPS := d e f
output_1:
mycommand $(FILE_1_DEPS) $#
output_2:
mycommand $(FILE_2_DEPS) $#
I would like to combine the multiple targets, which differ only by the name of the variable, into a single line (the FILE_%_DEPS being left as is). I am thinking something like the following, which does not work:
output_%:
mycommand $($(patsubst output_%, FILE_%_DEPS, $#)) $#
Easy enough, just look up Automatic Variables:
output_%:
mycommand $(FILE_$*_DEPS) $#
I am trying to evaluate a make variable which name is stored in another variable but it is not evaluating. Below is simplified version of my problem:
VAR=MYDEV
MYDEV_init=UART_init
define create_kernels_c
dev=$$(echo MYDEV); #this is mandatory code, simplified here
echo dev = $$dev;
initfn=$$dev\_init;
echo initfn= $$initfn
devinit=$($$initfn)
echo devinit= $$devinit
endef
.ONESHELL:
all:
#$(call create_kernels_c)
I want to evaluate $$devinit to UART_init, but it is not evaluating. What mistake I am making in my code?
I have this string cccccc:dddddd
I want to get cccccc only
I looked at makefile docs but still confused how to do this with make functions
This doesn't work but I want to do something like match from : to end of line and trim all of that
MY_VAR:=cccccc:dddddd
....
derp:
echo $(subst :.*,"",$(MY_VAR))
:dddddd is not static so I cant just hardcode that in like $(subst :dddddd,"",$(MY_VAR))
You can try something like:
MY_VAR := $(firstword $(subst :, ,$(MY_VAR))
Note this requires that "cccccc" does not contain whitespace.
I'm working on a Makefile which needs to be able to do the following:
From a user given variable, SRVS, containing file names, e.g.,
SRVS=Test1.java,test2.c,test3.c,test4.java,test5.c
produce a list of all files with a certain extension to be used by a foreach loop.
This list should not contain the extension anymore.
Currently, I can parse and get all the files into a usable list, but am unable to do so for an extension.
What I have:
$(foreach SRV, $(shell echo $(SRVS) | tr ',' ' '), \
CLASSPATH=$(SELF)/default_runtime javac $(UJ_DIR)/services/java/$(SRV).java && \
find $(UJ_DIR)/services/java/ -iname "$(SRV).class" -type f >> $(SELF)/files && \
) true
Which will take a list of SRVS and produce list usable by foreach and the code therein. For instance, the above example would result in "test1 test2 test3 test4 test5" to be used by the foreach loop
I'd like now to specify the extension, for instance .c, so that the above example would result in "test2 test3 test5".
Can you help me out?
First, you do not need to call shell (this is uselessly slow) because there are make built-in functions that do what you want. If, in the definition of variable SRVS you really cannot separate your file names with spaces (the standard make word separator) instead of commas, subst can do it for you. But there is a little trick because the comma is itself the arguments separator of make functions:
comma := ,
SRVS1 := $(subst $(comma), ,$(SRVS))
Next, filter is the make function that allows to select files by extension:
SRVS2 := $(filter %.c,$(SRVS1))
And finally, basename removes the suffix:
SRVS3 := $(basename $(SRVS2))
Demo:
$ cat Makefile
SRVS=Test1.java,test2.c,test3.c,test4.java,test5.c
comma := ,
SRVS1 := $(subst $(comma), ,$(SRVS))
SRVS2 := $(filter %.c,$(SRVS1))
SRVS3 := $(basename $(SRVS2))
all:
$(info SRVS1 = $(SRVS1))
$(info SRVS2 = $(SRVS2))
$(info SRVS3 = $(SRVS3))
$ make -q
SRVS1 = Test1.java test2.c test3.c test4.java test5.c
SRVS2 = test2.c test3.c test5.c
SRVS3 = test2 test3 test5
Or, all at once:
$ cat Makefile
TAGS := $(basename $(filter %.c,$(subst $(comma), ,$(SRVS))))
all:
$(info TAGS = $(TAGS))
$ make -q
TAGS = test2 test3 test5
My question concerns GNU's make.
If you have a sequence of commands that are useful as a recipe for several targets, a canned recipe comes in handy. I might look like this:
define run-foo
# Here comes a
# sequence of commands that are
# executed line by line
endef
Now you can use the canned recipe like this:
file1: input1:
$(run-foo)
$(pattern) : sub/% : %.inp
$(run-foo)
and so on. I wonder if it is possible to define canned recipes (or something similar) that take parameters, so that I could execute them like this:
file2: input2
$(run-foo) specific-parameter2 "additional"
file3: input3
$(run-foo) another-parameter3 "text"
Is this possible? Any hints welcome :)
You do this by:
Using parameters $1,$2... etc in your define-ed macro
Invoking the macro via $(call ...)
e.g:
define recipe
echo $1
endef
all: t1 t2
t1:
$(call recipe,"One")
t2:
$(call recipe,"Two")
Nearly 8 years. Okay, Necromancer mode on.
Despite answer by Mike Kinghan mitigates an issue, there's a solution for exact thing being asked.
Almost no black magic takes precedence here.
Simple example for an idea to be clear; just prints out all args:
define myrecipe-args
dummy() { printf 'arg: %s\n' "$$#"; }; dummy
endef
mytarget:
$(myrecipe-args) foo bar baz
Complex example, prints out automatic variables as well as args:
define myrecipe-full
_() { \
printf '$$# (target): %s\n' $#; \
printf '$$< (first prereq): %s\n' $<; \
printf '$$^ (all prereqs):'; printf ' %s' $^; echo; \
printf '$$| (order-only prereqs):'; printf ' %s' $|; echo; \
printf 'argv[]: %s\n' "$$#"; \
}; _
endef
mytarget : pa pb | oa ob
$(myrecipe-full) groovy defaulty targetty
#echo finally made $#!
pa pb oa ob:
#echo dummy: $#
As you can see it's just cheating on shell functions.
The downside, however, is a requirement for recipe to be one-liner.