Bad conversion of integer into a string using integer'image - vhdl

Question

I have a problem in my VHDL code. The function integer'image doesn't work properly. In the top of the project I call an entity (region_engine) with two "generate", this is the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use std.textio.all;
.....
ENGINE_ROW:
for i in 1 to sqrt_REGIONS_NUMBER generate
begin
ENGINES_COL:
for j in 1 to sqrt_REGIONS_NUMBER generate
begin
ENGINE_REGION_inst: entity work.region_engine
PORT MAP
( CLOCK => CLOCK,
RESET => RESET,
HITDATA => hitdata_region(4*(i-1)+j-1),
DV => data_valid((i-1)*sqrt_REGIONS_NUMBER + j-1),
BUSY_MAX => busy_red,
CLKEN => CLKEN_ACC,
number_i => (i-1),
number_j => (j-1),
ECS_BUS => ECS
);
end generate ENGINES_COL;
end generate ENGINE_ROW;
I pass the index i and j through number_i, number_j defined as integer. Here the code of
region_engine :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use std.textio.all;
entity region_engine is
port
(
CLOCK : in std_logic;
RESET : in std_logic;
HITDATA : in std_logic_vector(DATA_ENGINE-1 +4 downto 0);
DV : in std_logic;
BUSY_MAX : in std_logic;
CLKEN : in std_logic; ---forse non serve
number_i : in integer;
number_j : in integer;
ECS_BUS : in std_logic_vector(31 downto 0)
);
end entity region_engine;
....
ENGINEs_row :
for k in 0 to 3 generate
begin
ENGINEs_col:
for m in 0 to 3 generate
constant romfile_weight : string := "E:\Work\LHCb_Tesi\enginetoy_IT_test_allweight\lut_engine\peso_it\weight_engine_" & integer'image(16*number + k) & ".hex";
constant romfile_intersect : string := "E:\Work\LHCb_Tesi\enginetoy_IT_test_allweight\lut_engine\intersection_it_256\intersect_engine_" & integer'image(4*number_i + k) & "_" & integer'image((4*number_j + m)) &".hex";
begin
engine_inst : entity work.engine
GENERIC MAP
(
ENGINE_WEIGHT_FILE => romfile_weight,
ENGINE_INTERSECT_FILE => romfile_intersect
)
PORT MAP
(
CLOCK => CLOCK,
RESET => RESET,
HITDATA => c2(4*k + m)(DATA_ENGINE -1 downto 0),--HITDATA(i)(DATA_ENGINE -1 downto 0),--
ACC_RESET => acc_rst,--ed, --EE_delay,
ACC_EN => g,--e,--
ECS_DATA => ECS_BUS(DATA_ENGINE -1 downto 0),
INTERSECT_ADD => address(4*k +m),
WRITE_EN => w_en,--(i),
ACC_ENG => acc_16_eng(4*k + m)
);
end generate ENGINEs_col;
end generate ENGINEs_row;
I would like to pass to entity engine a file called intersect_engine_x_y.hex. Because of the previously range of indexes, the value
4*number_i + k and 4*number_j +m
should has a range from 0 to 15. But if I try to simulate the code with modelsim-altera these values don't match with the ones that I expect, in particulary the value 4*number_i - 4*number_j are put to zero.
Instead if I put in the string just number_i, number_j, as follow
constant romfile_intersect : string := "E:\Work\LHCb_Tesi\enginetoy_IT_test_allweight\lut_engine\intersection_it_256\intersect_engine_" & integer'image(number_i) & "_" & integer'image((number_j)) &".hex";
I read in modelsim this string:
"E:\Work\LHCb_Tesi\enginetoy_IT_test_allweight\lut_engine\intersection_it_256\intersect_engine_-2147483648_-2147483648.hex"
I don't know the reason for this behaviour, is it possible some trouble with the function integer'image?
Thanks for the help.

Answer 1

The index values i and j should be passed to region_engine through generics,
and not ports, so change the entity to:
entity region_engine is
generic (
NUMBER_I : integer;
NUMBER_J : integer);
port (
CLOCK : in std_logic;
RESET : in std_logic;
DV : in std_logic;
BUSY_MAX : in std_logic;
CLKEN : in std_logic; -- Force non serve
ECS_BUS : in std_logic_vector(31 downto 0));
end entity region_engine;
The generate should be changed accordingly to:
ENGINE_ROW :
for i in 1 to sqrt_REGIONS_NUMBER generate
begin
ENGINES_COL :
for j in 1 to sqrt_REGIONS_NUMBER generate
begin
ENGINE_REGION_inst : entity work.region_engine
generic map (
NUMBER_I => (i-1),
NUMBER_J => (j-1))
port map (
CLOCK => CLOCK,
RESET => RESET,
HITDATA => hitdata_region(4*(i-1)+j-1),
DV => data_valid((i-1)*sqrt_REGIONS_NUMBER + j-1),
BUSY_MAX => busy_red,
CLKEN => CLKEN_ACC,
ECS_BUS => ECS);
end generate ENGINES_COL;
end generate ENGINE_ROW;
The reason you see the value -2147483648 used for number_i in the other case,
is that the number_i is uninitialized at the time of use, as a result of the
VHDL execution model, thus having the lowest integer value (integer'low),
which is -2**31. So integer'image gives the expected result.
Btw. using both the standard IEEE package numeric_std and the non-standard
packages (actually Synopsys proprietary) std_logic_arith is very likely to
cause problems since e.g. unsigned is declared in both. So you may consider
removing all the std_logic_arith, and only using numeric_std.