Is it possible to build program with header files in another directories using makefile?
For example, I have some file (named client.cc), that contain:
...
#include "talk/examples/peerconnection/client/conductor.h"
#include "talk/examples/peerconnection/client/main_wnd.h"
...
This includes are in another directory. How I can add it to my makefile?
At this moment, I have Makefile, that contain:
CXX=arm-none-linux-gnueabi-g++
INC=-I/home/footniko/my/webrtcnative/trunk/
TARGET=$(shell basename `pwd`)
SOURCES=$(wildcard *.cc)
OBJECTS=$(SOURCES:%.cc=%.o)
all: $(TARGET)
$(OBJECTS): $(SOURCES)
$(TARGET): $(OBJECTS)
$(CXX) -o $(TARGET) $(LDFLAGS) $(INC) $(OBJECTS) $(LOADLIBES) $(LDLIBS)
clean:
$(RM) $(OBJECTS) $(TARGET)
.PHONY: all clean
Where /home/footniko/my/webrtcnative/trunk/ - is an absolute path to my headers. But when I'm trying to make, have this error:
client.cc:28:59: fatal error: talk/examples/peerconnection/client/conductor.h: No such file or directory
You could add that directory through CPPFLAGS which will be passed to the preprocessor,
CPPFLAGS = -I/home/footniko/my/webrtcnative/trunk/
Related
I'm trying to create a makefile for a very basic c++ program. I'm trying to implement the automatic generation of dependencies by running g++ with the -M flag, storing this output in a .d file, and then including those .d files in my main makefile. The makefile content is below
CC=g++
CPPFLAGS=-Wall -Wextra -g -std=c++11
SOURCEDIR=src
SOURCES = $(wildcard $(SOURCEDIR)/*.cpp)
BUILDDIR=build
OBJDIR=$(BUILDDIR)/objs
OBJS=$(SOURCES:$(SOURCEDIR)/%.cpp=$(OBJDIR)/%.o)
DEP_FILES = $(OBJS:.o=.d)
OUTFILE=hello.out
$(OUTFILE) : $(OBJS)
$(CC) -o $# $^ $(CPPFLAGS)
include $(DEP_FILES)
$(OBJDIR)/%.d : $(SOURCEDIR)/%.cpp
$(CC) $(CPPFLAGS) $< -MM -MT $(#:.d=.o) > $#
$(DEP_FILES) : | $(OBJDIR)
$(OBJS): | $(OBJDIR)
$(OBJDIR):
mkdir -p $(OBJDIR)
.PHONY: clean
clean:
rm -f $(BUILDDIR) -r
rm -f *~
rm -f $(OUTFILE)
When I run make, the directory build/objs/ is generated and a .d file is generated with rules in it. Here's main.d file:
build/objs/main.o: src/main.cpp src/main.h
And here's the myfunc.d file:
build/objs/myfunc.o: src/myfunc.cpp src/main.h
Here's the issue
Since I'm calling include on these .d files, I'd expect the .o files which they specify to then be created, and then the main outfile to be created as the main rule. However, make creates the .d files, and then skips directly to the main compilation step without creating any .o files:
g++ -o hello.out build/objs/myfunc.o build/objs/main.o -Wall -Wextra -g -std=c++11
This fails with the following error, since the .o files are never created:
g++: error: build/objs/myfunc.o: No such file or directory
g++: error: build/objs/main.o: No such file or directory
g++: fatal error: no input files
How can I use this makefile to generate the .o files necessary for g++? Thank you for any help in advance!
I saw you got your makefile working but I just wanted to add a few things you might want to consider for future projects. I recommend using the vpath variable rather than specifying $(OBJDIR)/%.o in your makefile recipes. I actually read somewhere that it's not "cannon" to build object files in a separate directory, but in the cursory search I conducted before posting, I couldn't find the document.
That being said, I wrote a makefile that does what you wanted; it builds the output folder, generates the dependencies, and compiles the program. I specifically included the $(COMPILE.cpp) definition so you could see what it's composed of. $(CC) is specifically the C compiler, and $(CFLAGS) is specifically flags for the C compiler. They're just variables, obviously, so you can change them like you did and it will work fine, but the main think to keep in mind is that whoever uses your programs will expect to be able to configure the compilation as they see fit. This means they will set the $(CXX) and $(CXXFLAGS) expecting to set the C++ compiler and flags. $(CPPFLAGS) stands for C/C++ Preprocessor flags.
It's not the cleanest makefile, and if I was to change something, I would just compile the object files in place and save myself that headache. That cuts down on unnecessary make hacking, but for the purposes of answering your question, here it is. Anyways I hope this helps you somewhat, let me know if you have any questions.
Oh yea, I almost forgot; notice I changed your make clean script. I used $(RM) instead of simply rm -f. When you use utilities in your makefiles, you want to use them as variables. Again, this is to allow your users as much freedom and flexibility as possible when they're compiling your program.
vpath %.cpp src
vpath %.hpp include
vpath %.o build/objs
vpath %.d build/objs
.SUFFIXES:
.SUFFIXES: .cpp .hpp .o .d
SRCDIR = src
INCLUDESDIR = include
BUILDDIR = build
OBJDIR = $(BUILDDIR)/objs
SRCS = $(wildcard $(SRCDIR)/*.cpp)
OBJS = $(patsubst %.cpp, %.o, $(notdir $(SRCS)))
DEP_FILES = $(patsubst %.o, %.d, $(OBJS))
INCLUDE_DIRS = -I $(INCLUDESDIR)
CXX = g++
CPPFLAGS =
CXXFLAGS = -Wall -Wextra -g -std=c++11
PROGRAM = hello.out
COMPILE.cpp = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(INCLUDE_DIRS) $(TARGET_ARCH)
all: $(PROGRAM)
$(PROGRAM): %: $(OBJS)
$(LINK.cpp) $(INCLUDE_DIRS) $(addprefix $(OBJDIR)/, $^) $(LOADLIBES) $(LDLIBS) -o $#
%.o: %.cpp
$(COMPILE.cpp) -c -o $(OBJDIR)/$# $<
%.d: %.cpp
mkdir -p $(OBJDIR)
$(COMPILE.cpp) $^ -MM -MT $(addprefix $(OBJDIR)/, $(#:.d=.o)) > $(OBJDIR)/$#
include $(DEP_FILES)
.PHONY: clean
clean:
#echo $(RM)
$(RM) $(BUILDDIR) -r
$(RM) *~
$(RM) $(PROGRAM)
For anyone having a similar issue, here's the correct solution is in the comments. Here for convenience: The included .d files generate dependencies but not a recipe for making the .o files, and since I'm putting things in various directories the default rule doesn't work here, so the .o files aren't created. The solution was to add in the following rule to my main makefile.
$(OBJDIR)/%.o :
$(CC) -c -o $# $< $(CPPFLAGS)
Thanks Matt and Renaud for your answers!
I am new to makefiles. My current makefile looks like this:
FC=ifort
FFLAGS=-c -module mod/
LDFLAGS=
SOURCES=$(wildcard src/*.f90)
OBJECTS=$(addprefix obj/, $(notdir $(SOURCES:.f90=.o)))
EXECUTABLE=RUN
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(FC) $(LDFLAGS) $^ -o $#
obj/%.o: src/%.f90
$(FC) $(FFLAGS) $< -o $#
The problem is my module files have names start with s and p which are usually compiled in the end of the list, and this causes problems when I have some changes in these module files. I am wondering what is the easiest way to compile these module files first? Yes I can change my module file directory to mod/ and set variables:
MODULES=$(wildcard mod/*.f90)
MODULE_OBJECTS=$(addprefix obj/, $(notdir $(MODULES: .f90=o)))
then add
$(MODULE_OBJECTS):$(MODULES)
$(FC) $(FFLAGS) $< -O $#
But, is there other ways to do this?
GNU Make 3.82
gcc 4.7.2
c89
I have the following make file:
INC_PATH=-I/home/dev_tools/apr/include/apr-1
LIB_PATH=-L/home/dev_tools/apr/lib
LIBS=-lapr-1 -laprutil-1
RUNTIME_PATH=-Wl,-rpath,/home/dev_tools/apr/lib
CC=gcc
CFLAGS=-Wall -Wextra -g -m32 -O2 -D_DEBUG -D_THREAD_SAFE -D_REENTRANT -D_LARGEFILE64_SOURCE $(INC_PATH)
SOURCES=$(wildcard src/*.c)
OBJECTS=$(patsubst %.c, %.o, $(SOURCES))
EXECUTABLE=bin/to
all: build $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(CFLAGS) -o $# $(RUNTIME_PATH) $(OBJECTS) $(LIB_PATH) $(LIBS)
$(OBJECTS): $(SOURCES)
$(CC) $(CFLAGS) -c $(SOURCES) $(LIB_PATH) $(LIBS)
build:
#mkdir -p bin
clean:
rm -rf $(EXECUTABLE) $(OBJECTS) bin
find . -name "*~" -exec rm {} \;
find . -name "*.o" -exec rm {} \;
My directory structure is like this project/src project/bin. My Makefile is in the project (root) folder, and all my *.h and *.c are in the src directory. Currently I have only one source file called timeout.c
I get this error:
gcc: error: src/timeout.o: No such file or directory
I have used this to get all the source files:
SOURCES=$(wildcard src/*.c)
And the object files:
OBJECTS=$(patsubst %.c, %.o, $(SOURCES))
However, the make seems to create the object file in the project root folder where the Makefile is. Should it not put it in the src directory?
You have two problems in this rule (well, three):
$(OBJECTS): $(SOURCES)
$(CC) $(CFLAGS) -c $(SOURCES) $(LIB_PATH) $(LIBS)
You haven't noticed yet, but the rule makes each object dependent on all sources, and tries to build that way. Not a problem as long as you have only one source. Easy to fix with a static pattern rule and an automatic variable:
$(OBJECTS): src/%.o : src/%.c
$(CC) $(CFLAGS) -c $< $(LIB_PATH) $(LIBS)
Also, the command ("$(CC)...") doesn't specify an output file name, so gcc will infer it from the source file name; if you give it src/timeout.c, it will produce timeout.o (in the working directory, project/). So you should specify the desired path to the output file. Easy to do with another automatic variable:
$(OBJECTS): src/%.o : src/%.c
$(CC) $(CFLAGS) -c $< $(LIB_PATH) $(LIBS) -o $#
Use gcc's -o option to write the output file to a particular location. For instance, you could say:
$(CC) $(CFLAGS) -c $(SOURCES) $(LIB_PATH) $(LIBS) -o $(OBJECTS)
Unfortunately, there's a problem with this line: if there is more than one source file in $(SOURCES), it won't work, since $(OBJECTS) will also contain multiple file names, and the -o option only binds to the first argument.
A way to compile each file in a list of source code files is to use implicit rules. In gmake, you would write:
$(EXECUTABLE): $(OBJECTS)
$(CC) $(CFLAGS) -o $# $(RUNTIME_PATH) $(OBJECTS) $(LIB_PATH) $(LIBS)
%.o : %.c
$(CC) $(CFLAGS) -c $< -o $#
where $< is replaced with name of the input file and $# is replaced with the name out the output file.
I solved this request and here is my Makefile and directory tree.
PROJECT := main.exe
DIR_SRC += .
DIR_SRC += ./src
DIR_INC += -lpthread
DIR_INC += -I./inc
DIR_INC += $(addprefix -I, $(DIR_SRC))
SRC_C += $(wildcard $(addsuffix /*.c, $(DIR_SRC)))
#OBJ := $(filter %.o, $(SRC_C:.c=.o))
OBJ := $(patsubst %.c, %.o, $(SRC_C))
EXE := $(PROJECT)
CC_PREFIX :=
CC := $(CC_PREFIX)gcc
CFLAG =
CLIB = -L .
.PHONY:all
all:$(OBJ) $(EXE)
%.o: %.c
$(CC) $(CFLAG) $(DIR_INC) -c $< -o $#
$(EXE): $(OBJ)
$(CC) $(CFLAG) $(CLIB) $(OBJ) -o $#
clean:
rm -r $(EXE) $(OBJ)
See my directory tree:
I have a lib (say mylib) and two executables and one of these (say exe1) depends on lib. In file system i have:
src
Makefile
...
lib
mylib
Makefile
...
exe1
Makefile
...
exe2
Makefile
...
and by launching make in src dir all is builded.
Makefile in src:
EXE=exe1 exe2
LIB=mylib
all: $(LIB) $(EXE)
.PHONY: $(LIB) $(EXE)
$(LIB):
$(MAKE) -C lib/$#
$(EXE): $(LIB)
$(MAKE) -C $#
and, for example, Makefile for exe1 is:
...
all: exe1 copy
exe1: exe1.o
$(CC) $(CFLAGS) $(OBJ) $(LDFLAGS) -o $#
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
...
My problem is that if i change a file in mylib dir the library is correctly rebuilded but exe1 obsiously no...is there a way to teel make that exe1 target depends on a target (mylib) that is specified in a previous invocation of make without specifing dependencies on mylib's files in exe1 Makefile?
Thank you all.
#tripleee and #JackKelly (curse his name) are right, this is not a healthy makefile system.
You can get something like what you want by changing src/Makefile:
EXE=exe1 exe2
LIB=lib/mylib/mylib
all: $(LIB) $(EXE)
.PHONY: $(EXE)
$(LIB):
$(MAKE) -C lib/mylib
exe1: $(LIB)
$(EXE):
$(MAKE) -C $#
and changing exe1/makefile so that it will always rebuild exe1:
.PHONY: exe1
This still has many problems, but at least it will correctly rebuild lib/mylib/mylib and src/exe1/exe1 when you run Make in src. (It will not work if you run Make in src/exe1/.)
I have several C and C++ projects that all follow a basic structure I've been using for a while now. My source files go in src/*.c, intermediate files in obj/*.[do], and the actual executable in the top level directory.
My makefiles follow roughly this template:
# The final executable
TARGET := something
# Source files (without src/)
INPUTS := foo.c bar.c baz.c
# OBJECTS will contain: obj/foo.o obj/bar.o obj/baz.o
OBJECTS := $(INPUTS:%.cpp=obj/%.o)
# DEPFILES will contain: obj/foo.d obj/bar.d obj/baz.d
DEPFILES := $(OBJECTS:%.o=%.d)
all: $(TARGET)
obj/%.o: src/%.cpp
$(CC) $(CFLAGS) -c -o $# $<
obj/%.d: src/%.cpp
$(CC) $(CFLAGS) -M -MF $# -MT $(#:%.d=%.o) $<
$(TARGET): $(OBJECTS)
$(LD) $(LDFLAGS) -o $# $(OBJECTS)
.PHONY: clean
clean:
-rm -f $(OBJECTS) $(DEPFILES) $(RPOFILES) $(TARGET)
-include $(DEPFILES)
Now I'm at the point where I'm packaging this for a Debian system. I'm using debuild to build the Debian source package, and pbuilder to build the binary package. The debuild step only has to execute the clean target, but even this causes the dependency files to be generated and included.
In short, my question is really: Can I somehow prevent make from generating dependencies when all I want is to run the clean target?
The solution is easy, don't -include generated files under clean:
ifneq ($(MAKECMDGOALS),clean)
-include $(DEPFILES)
endif