I need to parse a string inside a Makefile and fetch the value assigned to the variable parsed in the string.
String contains this data "Days=false;export Day;EXTRACT=true;export EXTRACT".
First i need to check if a variable(for eg Days) is present in the string.if it exists want to get the value of the variable.
i tried findstring function i can verify variable is present in string but i find how to get the value assigned to the variable.str1 := Days='true';export Days;EXTRACT=true;export EXTRACT;
a := $(findstring Days=, $(str1))
str1 := Days='true';export Days;EXTRACT=true;export EXTRACT;
define VARIABLE_EQ_VALUE_IN_STRING
$(eval $(filter $1=%, $(subst ;, ,$2)))
endef
$(call VARIABLE_EQ_VALUE_IN_STRING,Days, $(str1))
After this code, $(Days) is 'true'
On the other hand, if str1 did not contain an assignment to Days then after this code, Days would be undefined.
Related
We are facing a slightly weird problem in GNU Make.
In one of the part Makefile, we try to modify a string in order to get right filename.
So "dummy_1_.pl" is to converted to "dummy_1.pl".
We tried to use following way :-
MY_STRING := dummy_1_.pl
UNDPL := _.pl
DPL := .pl
$(subst $(UNDPL), $(DPL), $(MY_STRING) )
Surprisingly it doesn't work. We can replace ".", "pl", ".pl" etc all this way. However just "" or "." or "_.pl" etc replacement strings starting with an underscore doesn't seem to work.
Is underscore a special character in Make. Are we missing something basic here... We are at GNU Make 3.81
Any help/thought is highly appreciated. Thanks in advance!.
EDIT :-
The problem was posted in short for focused discussion. It seems, the details are necessary. This applies to a pattern rule as below. There's a OUT_V_FILES target that contains *blah_cpu.v *foo_gpu.v etc various target files. (The special string "cpu", "gpu" etc are part of a list.) We want to derive blah.pl, foo.pl respectively as input file for the rule.
DEVICES := cpu gpu memc dram
MY_STRING := $$(foreach dev,$(DEVICES),$$(subst $$(dev),$(NOTHING),$$(notdir %.pl)))
NOTHING :=
UDOT := _.
DOT := .
$(OUT_V_FILES) : %.v : $(subst $(UDOT),$(DOT),S(MY_STRING)) Makefile
#Body of rule+++++++++
There are two problems here. 1) you never assign the result of the $(subst ... invocation and 2) you have to be aware that whitespace is significant within the context of string manipulation functions. With that in mind your makefile code should be something like...
MY_STRING := $(subst $(UNDPL),$(DPL),$(MY_STRING))
In your updated example, it looks like you have some issues when setting MY_STRING. If you correct it to have the proper filename(s), you get:
MY_STRING := $$(foreach dev,$(DEVICES),$$(subst $$(dev),$(NOTHING),$$(notdir %.pl)))
$(info 1. MY_STRING=$(MY_STRING))
MY_STRING := dummy_1_.pl
$(info 2. MY_STRING=$(MY_STRING))
NOTHING :=
UDOT := _.
DOT := .
MY_NEW_STRING=$(subst $(UDOT),$(DOT),$(MY_STRING))
$(info MY_NEW_STRING=$(MY_NEW_STRING))
gives
1. MY_STRING=$(foreach dev,cpu gpu memc,$(subst $(dev),,$(notdir %.pl)))
2. MY_STRING=dummy_1_.pl
MY_NEW_STRING=dummy_1.pl
If I have the following at the top of a gnu makefile:
$(if _,a:=1)
$(info a=$a)
Compilation fails (make-3.81: *** No rule to make target '=1', needed by 'a'. Stop., or *** missing separator. Stop. if I exclude the colon). I know I can get around this by using an eval, but I'm not understanding why it's required. Shouldn't this expand to a:=1, be parsed, and set a to 1?
I'm not understanding why it's required
Well, such is the design.
Evaluation procedure always performs a (recursive) expansion (except for "the initial evaluation" where subsequent expansion can be effectively stopped by =, i.e. "lazy assignment"), but expansion procedure never does evaluation, unless it's explicitly told so (basically, $(eval ...) is such an order to switch from expansion to evaluation).
Consider this:
x := 0
y := 1
# z is set to "y<space><equal><space><dollar>x"
z = y = $x
# [0] [1] [y = $x]
$(info [$x] [$y] [$(value z)])
# error as "y = $x" will not be re-evaluated
#$z
# effectively sets y to "0"
$(eval $z)
# [0] [0] [y = $x]
$(info [$x] [$y] [$(value z)])
From make's point of view $(if cond,x=y) does not differ much from $z --- it's expanded but not evaluated. No matter where it stands. Just think anything of a form $(...) to be "data", not "code".
In your case the if function evaluates as its second argument (a:=1) but this is not evaluated in turn as a make variable assignment. With your version of make it becomes a rule. This is probably due to the way make syntactically parses the makefiles. It does not consider that this if statement can be a variable assignment because (before expansion) it looks like none of the valid make variable assignments. So the if statement gets expanded but it is too late for make to consider the result as a variable assignment...
Instead you can use:
a := $(if _,1)
or:
ifneq (_,)
a := 1
endif
or:
$(if _,$(eval a := 1))
or:
$(eval $(if _,a := 1))
The two last forms work because by definition the result of the expansion of the argument of the eval function is processed as plain make statements.
Is it possible do the following in one $(call ...) inside a prerequisite list?
Assign an argument to a (private/non-inheriting) variable.
Add the argument to the target list.
That is, the following should assign the string value to the variable $(var), while adding value as a prerequisite for the target foo.
foo: $(call assign-value-to-var,value)
# Do stuff
Yeah, why not?
assign-value-to-var=$(eval foo: private var:=$1)$1
foo: $(call assign-value-to-var,value)
# Do stuff
I want to filter out a pattern as "-Wl, Bdynamic -lmylib" from a long LDFLAGS list. But filter-out function can only handle space-separated list, is there other method to do this in Makefile?
The only way to do it is by replacing spaces with some other character that you know doesn't appear in the variable value. For example suppose you know that the ^ character never appears in your variable value, then you can do something like this:
# Create a variable containing a space
E :=
S := $E $E
LDFLAGS := $(subst ^,$S,$(subst -Wl^Bdynamic^-lmylib,,$(subst $S,^,$(LDFLAGS))))
Am trying to match specific string after doing subst on a variable ; substitution is ok but while trying to match make returns error 127.
Does anyone know what's going on here ? why make should return error ?
$> make -f strsearch.mk
CODE : BBROY_OF_GREAT_BRITAIN_HAD_A_GREAT_WIFE
MORSE = BBROY OF GREAT BRITAIN HAD A GREAT WIFE
**make: MORSE: Command not found
make: * [search_new] Error 127
Here is the snippet of makefile:
VAR1 := BBROY_OF_GREAT_BRITAIN_HAD_A_GREAT_WIFE
search_new:
#echo CODE : $(VAR1)
MORSE = $(subst _, , $(VAR1))
#echo word count : ($words $(MORSE))
#echo After substitution Britain matches: $(filter %BRITAIN%, $(MORSE))
Your variable declaration is in the wrong place or form:
The form you use is for global assignment and cannot be inside a target block.
Either make it a global variable outside a target block
Or use the shell and eval to set the variable value. See the accepted answer for how to approach this issue: Define make variable at rule execution time
A 3rd option is to define the variable as a sort-of prerequisite which is then assigned at the time the dependencies are evaluated.