VHDL: CLA subtractor Module cascade - vhdl

Question

Good day,
I have implemented a 8 bit CLA add/subtract module and it works great. The code is below: I have strung 2 of these modules below to create a 16 bit adder/subtractor. This 16 bit version works great for addition, the carry is generated by 1 8 bit adder for the lower bits, which is then passed onto the next adder to be handled for the upper bits.
The problem is with subtraction. It doesn't work, even on paper. Let me give you an example. Lets say I want to do 350 - 50
300: 00000001 00101100
50: 00000000 00110010
Hence, if i let one adder handle the lower bits, and another handle the upper bits, it simply would not work. Here is why:
300: 00000001 00101100
50 in 2's compliment: 11111111 11001110
250 is supposed to be 00000000 11111010
1st adder: Generates correct value after addition 11111010. That's cool. Now the second adder, is a problem. It will do (1's compliment + 1) which will give 00000000 (with carry). It was supposed to be (11111111), but because of the + 1 in the algo which is a general implementation, it screws up the final answer.
By right, since Adder 0 has no carry, Adder 1 should not do the + 1. How might I be able to implement this in the logic for the general purpose 8 bit sub/adder? Is this the correct thinking and have i covered all possible fallouts/edge cases?
entity CLA_ADD_SUB is
generic (N : integer := 8);
Port ( A : in STD_LOGIC_VECTOR (N-1 downto 0);
B : in STD_LOGIC_VECTOR (N-1 downto 0);
Binv : in STD_LOGIC;
C_in: in STD_LOGIC;
S : out STD_LOGIC_VECTOR (N-1 downto 0);
TEST : out STD_LOGIC_VECTOR (N-1 downto 0);
C_out : out STD_LOGIC
);
end CLA_ADD_SUB;
architecture CLA_ADD_SUB_ARCH of CLA_ADD_SUB is
SIGNAL h_sum : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
SIGNAL carry_generate : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
SIGNAL carry_propagate : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
SIGNAL carry_in_internal : STD_LOGIC_VECTOR(N-1 DOWNTO 1);
SIGNAL B_mod : STD_LOGIC_VECTOR(N-1 DOWNTO 0) := B;
SIGNAL C_in_mod: STD_LOGIC := C_in;
signal S_wider : std_logic_vector(N downto 0);
begin
WITH Binv SELECT
B_mod <= B WHEN '0',
not B WHEN '1',
B WHEN OTHERS;
WITH Binv SELECT
C_in_mod <= C_in WHEN '0',
not C_in WHEN '1',
C_in WHEN OTHERS;
-- Sum, P and G
h_sum <= A XOR B_mod;
carry_generate <= A AND B_mod;
carry_propagate <= A OR B_mod;
PROCESS (carry_generate,carry_propagate,carry_in_internal,C_in_mod)
BEGIN
carry_in_internal(1) <= carry_generate(0) OR (carry_propagate(0) AND C_in_mod);
inst: FOR i IN 1 TO (N-2) LOOP
carry_in_internal(i+1) <= carry_generate(i) OR (carry_propagate(i) AND carry_in_internal(i));
END LOOP;
C_out <= carry_generate(N-1) OR (carry_propagate(N-1) AND carry_in_internal(N-1));
END PROCESS;
S(0) <= h_sum(0) XOR C_in_mod;
S(N-1 DOWNTO 1) <= h_sum(N-1 DOWNTO 1) XOR carry_in_internal(N-1 DOWNTO 1);
end CLA_ADD_SUB_ARCH;

Answer 1

The problem is, that you did an error calculating the 2's complement of 50:
In your equation you use:
50 in 2's compliment: 11111111 11001101 <--- WRONG.
which is just 50 with all bits inverted. two's complement however is build by first inverting the bits, then add one to it.
The correct representation of -50 in 16 bit integers is:
50 in 2's compliment: 11111111 11001110
If we now do the math of 300 - 50 we'll get:
00000001 00101100 | 300
+ 11111111 11001110 | -50 in 2's complement form
-------------------
00000000 11111010 | 250 (expected result)
For your VHDL implementation that means that you can implement subtraction by re-using the addition part. To do so build the two's complement in two steps:
If subtraction-mode:
negate all bits of B prior to addition
force the carry-in of the low 8 bit adder to high.
The second step will add the one to the negated B which then is a correct two's complement number. Now you add your numbers as usual and get a functional subtracter.

Answer 2

u_ADDER_0: entity work.CLA_ADD_SUB(CLA_ADD_SUB_ARCH)
port map(
A => ADDER_0_A, -- Bits 0-7
B => ADDER_0_B,
Binv => TOADD_BINV,
C_in => ADDER_0_CARRY_IN,
S => ADDER_0_SUM,
TEST => ADDER_0_TEST,
C_out => ADDER_0_CARRY_OUT
);
u_ADDER_1: entity work.CLA_ADD_SUB(CLA_ADD_SUB_ARCH)
port map(
A => ADDER_1_A, --Bits 7 to 15
B => ADDER_1_B,
Binv => TOADD_BINV,
C_in => TOADD_BINV xor ADDER_0_CARRY_OUT,
S => ADDER_1_SUM,
TEST => ADDER_1_TEST,
C_out => ADDER_1_CARRY_OUT
);
Ah I get it, actually what I did was for all subsequent adders (for bits 7-15 etc.) I set the Carry for those to (Binv xor Adder_0_Carry). Hence, if the 1st adder has a carry due to the + 1 for the 2's compliment, it will propogate out of the carry, and since I xor it with Binv, I tell the second adder to not add a carry.
the idea is that if we are subtracting (doing 2's compliment), we should just do a (1's compliment) if the first adder had no carry
I cannot confirm this for all test cases. This is just a theory and so far it seems to work

Answer 3

This is supplemental to your own answer.
Hmm..if I set B_inv to 0, meaning I am doing addition, and I pass in two signed bits. say 50 and -250, it won't work, because the second adder's C_in is determined by Binv xor Adder_0_carry
I think your manual arithmetic is faulty:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_add_sub_gang is
constant n: natural := 8;
end entity;
architecture foo of tb_add_sub_gang is
signal a: std_logic_vector (2*n-1 downto 0);
signal b: std_logic_vector (2*n-1 downto 0);
signal s: std_logic_vector (2*n-1 downto 0);
signal test: std_logic_vector (2*n-1 downto 0);
signal binv: std_logic;
signal cout0: std_logic;
signal cin1: std_logic;
signal cout1: std_logic;
begin
cin1 <= cout0 xor binv;
uadder0:
entity work.cla_add_sub(cla_add_sub_arch)
port map(
a => a((2*n-1)/2 downto 0), -- bits 0-7
b => b((2*n-1)/2 downto 0),
binv => binv,
c_in => '0',
s => s((2*n-1)/2 downto 0),
test => s((2*n-1)/2 downto 0),
c_out => cout0
);
uadder1:
entity work.cla_add_sub(cla_add_sub_arch)
port map(
a => a(2*n-1 downto n), --bits 8 to 15
b => b(2*n-1 downto n),
binv => binv,
c_in => cin1,
s => s(2*n-1 downto n),
test => test(2*n-1 downto n),
c_out => cout1
);
STIMULUS:
process
begin
wait for 100 ns;
a <= std_logic_vector(to_unsigned(350,a'length));
b <= std_logic_vector(to_unsigned(50,b'length));
binv <= '1';
wait for 100 ns;
binv <= '0';
wait for 100 ns;
a <= std_logic_vector(to_unsigned(50,a'length));
b <= std_logic_vector(to_unsigned(250,b'length));
binv <= '1';
wait for 100 ns;
binv <= '0';
wait for 600 ns;
wait;
end process;
end architecture;
Gives:
(I update the waveform image for your signed subtraction/addition).
The binv selector in cla_add_sub is the equivalent of XOR between Binv and C_in. XORing Binv in again externally for the Most Significant n bit adder is gives you an even number number of XORs removing their effect, carrying in the carry out of the Least Significant adder.
The proper thing to do is actually to only invert B with Binv and use Binv to also invert the carry in of the LS adder. Because you never carry in to it other than for subtraction, hook it directly to Binv. This will fix everything.
in cla_add_sub comment out:
-- WITH Binv SELECT
-- C_in_mod <= C_in WHEN '0',
-- not C_in WHEN '1',
-- C_in WHEN OTHERS;
The declaration for C_in_mod:
-- SIGNAL C_in_mod: STD_LOGIC := C_in;
And use C_in directly:
PROCESS (carry_generate,carry_propagate,carry_in_internal,C_in)
BEGIN
carry_in_internal(1) <= carry_generate(0) OR (carry_propagate(0) AND C_in);
inst: FOR i IN 1 TO (N-2) LOOP
carry_in_internal(i+1) <= carry_generate(i) OR (carry_propagate(i) AND carry_in_internal(i));
END LOOP;
C_out <= carry_generate(N-1) OR (carry_propagate(N-1) AND carry_in_internal(N-1));
END PROCESS;
And for S(0):
S(0) <= h_sum(0) XOR C_in;
In the top level:
-- signal cin1: std_logic;
-- cin1 <= cout0 xor binv;
uadder0:
entity work.cla_add_sub(cla_add_sub_arch)
port map(
a => a((2*n-1)/2 downto 0), -- bits 0-7
b => b((2*n-1)/2 downto 0),
binv => binv,
c_in => binv,
s => s((2*n-1)/2 downto 0),
test => s((2*n-1)/2 downto 0),
c_out => cout0
);
uadder1:
entity work.cla_add_sub(cla_add_sub_arch)
port map(
a => a(2*n-1 downto n), --bits 8 to 15
b => b(2*n-1 downto n),
binv => binv,
c_in => cout,
s => s(2*n-1 downto n),
test => test(2*n-1 downto n),
c_out => cout1
);
And that gives the same results as shown above.
And notice this is in keeping with Nils answer.
If you only had an n bit adder/subtractor you'd use the method in your answer where carry out (LS) to carry in (MS) would be inverted again to chain two 8 bit operations together.
This instantiates two adders that happen to invert B, the 1's complement part of 2's Complement to subtract 'B'. You could add an input to cla_add_sub signify when it's the LS adder and only XOR Binv then. That way it could serve as either a stand alone n bit adder or one that can be daisy chained.