Applying 7-segment display using counter VHDL - vhdl

Question

I am beginner and it's my first VHDL code
It's a code to apply 7_segment display using counter
When compiling the 2 codes the main code had no errors while the test bench code gave 6 errors
any help ?
Main code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY counter IS
port (clk,rst: IN std_logic;
count: OUT std_logic_vector(6 downto 0) );
END counter;
ARCHITECTURE rtl OF counter IS
signalcount_sig: integer range 0 to 7;
BEGIN
PROCESS(clk,rst)
begin
if(rst='1')then
count_sig<=0;
elsif(rising_edge (clk))then
count_sig<= count_sig+1;
end if;
if (count_sig=0) then count <= "1000000";
elsif (count_sig=1) then count <= "1111001";
elsif (count_sig=2) then count <= "0100100";
elsif (count_sig=3) then count <= "0110000";
elsif (count_sig=4) then count <= "0011001";
elsif (count_sig=5) then count <= "0010010";
elsif (count_sig=6) then count <= "0000010";
elsif (count_sig=7) then count <= "1111000";
end if;
end PROCESS;
END rtl;
Test bench code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY test_counter IS
END test_counter;
ARCHITECTURE beh OF test_counter IS
COMPONENT counter IS
port (clk, rst: in std_logic;
count: out std_logic_vector(6 downto 0));
END counter;
SIGNAL clk, rst: std_logic;
SIGNAL count: std_logic_vector(6 downto 0);
BEGIN
V1: counter PORT MAP
(clk<=clk ,
rst<=rst ,
count<=count);
clock : PROCESS
begin
wait for 5 ns; clk<= not clk;
end PROCESS clock;
reset : PROCESS
begin
rst<= '1';
wait for 10 ns; rst<= '0';
wait for 80 ns;
end PROCESS reset;
END beh;

Answer 1

In the test bench code, the component declaration end is not to be END counter; but:
END component counter;
or just:
END component;
For the component instantiation, then mapping from port name (formal) to signal (actual) does not use <= but =>, so the code instantiation should be:
V1: counter PORT MAP
(clk => clk,
rst => rst,
count => count);