How to escape parenthesis for the cp command inside a Makefile - bash

I have this Makefile:
VAR=foo(1).txt foo(2).txt
foobar: $VAR
cp -p $^ foo/
When I run it I get this error:
$ make test
/bin/sh: -c: line 0: syntax error near unexpected token `('
/bin/sh: -c: line 0: `cp -p foo(1).txt foo(2).txt foo/'
Makefile:3: recipe for target 'foobar' failed
make: *** [test] Error 1
How to quickly get rid of it?

You can wrapt the file names in double quotes
cp "foo(1).txt" "foo(2).txt" /out
Test
$ cp "foo(1).txt" "foo(2).txt" out/
$ ls out/
foo(1).txt foo(2).txt
Or much safer would be
cp 'foo(1).txt' 'foo(2).txt' out/

Related

syntax error near unexpected token '(' in bash script when selecting files [extend]

Question similar to here, but for my use case, I'd like to place inside the makefile.
#!/bin/bash
# Example:
# make run TEST_CASE="testbench.sv"
# make clean
compile:
vcs $(TEST_CASE) -sverilog;
run: compile
./simv
uvm_compile:
vcs $(TEST_CASE) -sverilog;
clean:
shopt -s extglob;
rm -v !(*.sv|*svh|"makefile");
The problem exist in make clean, and I got the following result:
ycliao#localhost:[~/workspace/i2c_vip/uvm_practice]: make clean
shopt -s extglob;
rm -v !(*.sv|*svh|"makefile");
/bin/sh: -c: line 0: syntax error near unexpected token `('
/bin/sh: -c: line 0: `rm -v !(*.sv|*svh|"makefile");'
make: *** [clean] Error 1
As I understand makefiles, every line is executed in a separate shell. So you need to add a line continuation to concatenate the commands so that they execute in the same shell:
SHELL = /bin/bash
# ...
clean:
shopt -s extglob; \
rm -v !(*.sv|*svh|"makefile");
This is demonstrated in Example makefiles on the wikipedia Make page.
I believe the problem is a bash problem. For some reason, it doesn't seem possible to do shopt followed by some command as a one-liner. Let's take make completely out of the picture. In a bash shell:
$ ls -1 /tmp/hosts.tar.*
/tmp/hosts.tar.bz2
/tmp/hosts.tar.gz
$ shopt -s extglob ; ls -1 /tmp/hosts.tar.#(bz2|gz)
bash: syntax error near unexpected token `('
$ ls -1 /tmp/hosts.tar.#(bz2|gz)
bash: syntax error near unexpected token `('
$ shopt -s extglob
$ ls -1 /tmp/hosts.tar.#(bz2|gz)
/tmp/hosts.tar.bz2
/tmp/hosts.tar.gz
To Sum up, for the makefile, it is not allow to have this.
ycliao#localhost:[~/workspace/i2c_vip/uvm_practice]: make clean
shopt -s extglob; \
rm -v !(*.sv|*svh|"makefile");
/bin/bash: -c: line 1: syntax error near unexpected token `('
/bin/bash: -c: line 1: `rm -v !(*.sv|*svh|"makefile");'
make: *** [clean] Error 1

Syntax error in Makefile: end of file unexpected (expecting "fi")

Here is my make target:
copy_python:
if test -d $(VIRTUAL_ENV)/lib; then \
cp -a $(VIRTUAL_ENV)/lib/python2.7/site-packages/. ./package/tmp/; \
fi
if test -d $(VIRTUAL_ENV)/lib64; then \
cp -a $(VIRTUAL_ENV)/lib64/python2.7/site-packages/. ./package/tmp/; \
fi
Here is the error:
/bin/sh: 2: Syntax error: end of file unexpected (expecting "fi")
Makefile:28: recipe for target 'copy_python' failed
make: *** [copy_python] Error 2
Why does this error occur?
You have an extra space after the ending backslash, at the end of the second cp command. For this reason, \ no longer acts as a line continuation and the fi on the next line is not passed to sh

Check existence of a directory in Makefile

I want that my Makefile creates a directory if it doesn't already exist on OS X. Otherwise I would use mkdir -p, but it deletes whatever the directory already contains and I don't want that. Here's what I've tried so far:
all:
DIR=../../aether3d_build
ifneq ("$(wildcard $(DIR))","")
mkdir $(DIR)
endif
It causes the following error:
DIR=../../aether3d_build
ifneq ("","")
/bin/sh: -c: line 0: syntax error near unexpected token `"",""'
/bin/sh: -c: line 0: `ifneq ("","")'

How to fix Makefile syntax error when using wildcard on make clean?

I have a simple Makefile that just contains this one target. It looks like this:
SHELL:=/bin/bash
clean:
rm !(*.tex|Makefile|*.pdf)
When I run this command in bash it works fine, i.e. it gives no errors and it removes the desired files. However when I run make clean it gives the following errors:
$ make clean
rm !(*.tex|Makefile|*.pdf)
/bin/bash: -c: line 0: syntax error near unexpected token `('
/bin/bash: -c: line 0: `rm !(*.tex|Makefile|*.pdf)'
make: *** [clean] Error 1
Has anybody got an idea what I'm doing wrong? Thanks.
Change the SHELL line to
SHELL:=/bin/bash -O extglob
The extglob option is not set by default, so you have to do that yourself.

Makefile delete all files but one [duplicate]

I have a simple Makefile that just contains this one target. It looks like this:
SHELL:=/bin/bash
clean:
rm !(*.tex|Makefile|*.pdf)
When I run this command in bash it works fine, i.e. it gives no errors and it removes the desired files. However when I run make clean it gives the following errors:
$ make clean
rm !(*.tex|Makefile|*.pdf)
/bin/bash: -c: line 0: syntax error near unexpected token `('
/bin/bash: -c: line 0: `rm !(*.tex|Makefile|*.pdf)'
make: *** [clean] Error 1
Has anybody got an idea what I'm doing wrong? Thanks.
Change the SHELL line to
SHELL:=/bin/bash -O extglob
The extglob option is not set by default, so you have to do that yourself.

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