Please help me with checking this code for correcting error using hamming code in VHDL. I have being able to detect error but not correct it.
I have three modules my encoder, decoder and an error injector. I have a feeling it my decoder that is having issues. Below is my decoder code
library ieee;
use ieee.std_logic_1164.all;
entity hamdec8 is
port(
datain: in std_logic_vector (7 downto 0);
parin : in std_logic_vector(4 downto 0);
Dataout : out std_logic_vector(7 downto 0);
Parout : out std_logic_vector(4 downto 0);
NE : out std_logic;
DED : out std_logic;
SEC : out std_logic
);
Constant MaskP1 : std_logic_vector(7 downto 0) := "01011011";
Constant MaskP2 : std_logic_vector(7 downto 0) := "01101101";
Constant MaskP3 : std_logic_vector(7 downto 0) := "10001110";
Constant MaskP4 : std_logic_vector(7 downto 0) := "11110000";
end hamdec8;
architecture beh of hamdec8 is
signal synd : std_logic_vector(4 downto 1);
signal P0 : std_logic;
signal din1, din2, din3, din4 : std_logic_vector(7 downto 0); --to hold datain AND maskp
begin
process(Datain, Parin)
begin
NE <= '1';
DED <= '0';
SEC <= '0';
Dataout <= Datain;
Parout <= Parin;
P0 <= (Parin(0) XOR Parin(1) XOR Parin(2) XOR Parin(3) XOR
Parin(4) XOR Datain(0) XOR Datain(1) XOR Datain(2) XOR
Datain(3) XOR Datain(4) XOR Datain(5) XOR Datain(6) XOR
Datain(7));
din1 <= Datain AND MaskP1;
Synd(1) <= din1(0) XOR din1(1) XOR din1(2) XOR din1(3) XOR
din1(4) XOR din1(5) XOR din1(6) XOR din1(7) XOR Parin(1);
din2 <= Datain AND MaskP2;
Synd(2) <= din2(0) XOR din2(1) XOR din2(2) XOR din2(3) XOR
din2(4) XOR din2(5) XOR din2(6) XOR din2(7) XOR Parin(2);
din3 <= Datain AND MaskP3;
Synd(3) <= din3(0) XOR din3(1) XOR din3(2) XOR din3(3) XOR
din3(4) XOR din3(5) XOR din3(6) XOR din3(7) XOR Parin(3);
din4 <= Datain AND MaskP4;
Synd(4) <= din4(0) XOR din4(1) XOR din4(2) XOR din4(3) XOR
din4(4) XOR din4(5) XOR din4(6) XOR din4(7) XOR Parin(4);
if (synd = "0000") then
IF (P0 = '0') then
--Dataout <= Datain;
--NE <= '1';
--DED <= '0';
--SEC <= '0';
--Parout <= Parin;
null;
elsif (P0 = '1') then --single error
NE <= '0';
DED <= '0';
SEC <= '1';
case synd is
when "0000" => Parout(0) <= NOT Parin(0);
when "0001" => Parout(1) <= NOT Parin(1);
when "0010" => Parout(2) <= NOT Parin(2);
when "0011" => Dataout(0) <= NOT Datain(0);
when "0100" => Parout(3) <= NOT parin(3);
when "0101" => Dataout(1) <= NOT Datain(1);
when "0110" => Dataout(2) <= NOT Datain(2);
when "0111" => Dataout(3) <= NOT Datain(3);
when "1000" => parout(4) <= parin(4);
when "1001" => Dataout(4) <= NOT Datain(4);
when "1010" => Dataout(5) <= NOT Datain(5);
when "1011" => Dataout(6) <= NOT Datain(6);
when "1100" => Dataout(7) <= NOT Datain(7);
when others =>
Parout <= parin;
Dataout <= Datain;
end case;
Dataout <= "00000000";
Parout <= "00000";
end if;
elsif (P0 = '0') then
if (synd /= "0000") then
NE <= '0';
DED <= '1';
SEC <= '0';
Dataout <= "00000000";
Parout <= "00000";
end if;
end if;
end process;
end beh;
Thank you
The correction logic implemented in the case statement is only reached when the syndrome is "0000" and the overall parity is '1'. That doesn't cover all the other possible syndrome values. The indentation of the single-error elsif makes this confusing. You need to rework the nested if statements so that correction is applied for all syndromes.
Your signals P0, synd, din1, din2, din3, din4 should be declared as variables in the process or you should extract the xor calculation from process.
Second variant with extracted xor calculation, extended sensitivity list and fixed code indentation:
library ieee;
use ieee.std_logic_1164.all;
entity hamdec8 is
port (
datain: in std_logic_vector (7 downto 0);
parin : in std_logic_vector(4 downto 0);
Dataout : out std_logic_vector(7 downto 0);
Parout : out std_logic_vector(4 downto 0);
NE : out std_logic;
DED : out std_logic;
SEC : out std_logic
);
end hamdec8;
architecture beh of hamdec8 is
Constant MaskP1 : std_logic_vector(7 downto 0) := "01011011";
Constant MaskP2 : std_logic_vector(7 downto 0) := "01101101";
Constant MaskP3 : std_logic_vector(7 downto 0) := "10001110";
Constant MaskP4 : std_logic_vector(7 downto 0) := "11110000";
signal synd : std_logic_vector(4 downto 1);
signal P0 : std_logic;
signal din1, din2, din3, din4 : std_logic_vector(7 downto 0); --to hold datain AND maskp
begin
P0 <= Parin(0) XOR Parin(1) XOR Parin(2) XOR Parin(3) XOR Parin(4) XOR
Datain(0) XOR Datain(1) XOR Datain(2) XOR Datain(3) XOR Datain(4) XOR
Datain(5) XOR Datain(6) XOR Datain(7);
din1 <= Datain AND MaskP1;
din2 <= Datain AND MaskP2;
din3 <= Datain AND MaskP3;
din4 <= Datain AND MaskP4;
Synd(1) <= din1(0) XOR din1(1) XOR din1(2) XOR din1(3) XOR
din1(4) XOR din1(5) XOR din1(6) XOR din1(7) XOR Parin(1);
Synd(2) <= din2(0) XOR din2(1) XOR din2(2) XOR din2(3) XOR
din2(4) XOR din2(5) XOR din2(6) XOR din2(7) XOR Parin(2);
Synd(3) <= din3(0) XOR din3(1) XOR din3(2) XOR din3(3) XOR
din3(4) XOR din3(5) XOR din3(6) XOR din3(7) XOR Parin(3);
Synd(4) <= din4(0) XOR din4(1) XOR din4(2) XOR din4(3) XOR
din4(4) XOR din4(5) XOR din4(6) XOR din4(7) XOR Parin(4);
process(Datain, Parin, synd, P0)
begin
NE <= '1';
DED <= '0';
SEC <= '0';
Dataout <= Datain;
Parout <= Parin;
if (synd = "0000") then
IF (P0 = '0') then
--Dataout <= Datain;
--NE <= '1';
--DED <= '0';
--SEC <= '0';
--Parout <= Parin;
null;
elsif (P0 = '1') then --single error
NE <= '0';
DED <= '0';
SEC <= '1';
case synd is
when "0000" => Parout(0) <= NOT Parin(0);
when "0001" => Parout(1) <= NOT Parin(1);
when "0010" => Parout(2) <= NOT Parin(2);
when "0011" => Dataout(0) <= NOT Datain(0);
when "0100" => Parout(3) <= NOT parin(3);
when "0101" => Dataout(1) <= NOT Datain(1);
when "0110" => Dataout(2) <= NOT Datain(2);
when "0111" => Dataout(3) <= NOT Datain(3);
when "1000" => parout(4) <= parin(4);
when "1001" => Dataout(4) <= NOT Datain(4);
when "1010" => Dataout(5) <= NOT Datain(5);
when "1011" => Dataout(6) <= NOT Datain(6);
when "1100" => Dataout(7) <= NOT Datain(7);
when others => null;
end case;
--Dataout <= "00000000"; -- these lines override all calculations
--Parout <= "00000"; -- from previous case statement
end if;
elsif (P0 = '0') then
if (synd /= "0000") then
NE <= '0';
DED <= '1';
SEC <= '0';
Dataout <= "00000000";
Parout <= "00000";
end if;
end if;
end process;
end beh;
What's up with this code?
IF (P0 = '0') then
-- commented out stuff
[...]
null;
elsif (P0 = '1') then --single error
[...]
end if;
Why not just use:
if p0 = '1' then
[...]
end if;
or at least
if p0 = '0' then
[stuff for when p0 is '0']
else
[stuff for when p0 is not '0']
end if;
Related
This is what I am implementing.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sammy_2018314405 is
Port ( codeword : in STD_LOGIC_VECTOR (6 downto 0);
syndrome : out STD_LOGIC_VECTOR (2 downto 0);
dataword : out STD_LOGIC_VECTOR (3 downto 0));
end sammy_2018314405;
architecture Behavioral of sammy_2018314405 is
signal s : std_logic_vector(2 downto 0);
signal b3, b2, b1, b0, q2, q1, q0 : std_logic;
signal temp : std_logic_vector(6 downto 0);
begin
b3 <= codeword(6);
b2 <= codeword(5);
b1 <= codeword(4);
b0 <= codeword(3);
q2 <= codeword(2);
q1 <= codeword(1);
q0 <= codeword(0);
s(0) <= b0 xor b1 xor b2 xor q0;
s(1) <= b1 xor b2 xor b3 xor q1;
s(2) <= b0 xor b1 xor b3 xor q2;
temp <= (b3,b2,b1,b0,q2,q1,q0);
process(s)
begin
case s is
when "001" => temp(0) <= not temp(0);
when "010" => temp(1) <= not temp(1);
when "011" => temp(5) <= not temp(5);
when "100" => temp(2) <= not temp(2);
when "101" => temp(3) <= not temp(3);
when "110" => temp(6) <= not temp(6);
when "111" => temp(4) <= not temp(4);
when others => null;
end case;
end process;
syndrome(2 downto 0) <= s(2 downto 0);
dataword(3 downto 0) <= temp(6 downto 3);
end Behavioral;
--I get warnings that show temp should be on the sensitivity list of process. I do not understand what does this means. I should get a result something like the picture below.
Result for the implementation
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sammy_2018314405 is
Port ( codeword : in STD_LOGIC_VECTOR (6 downto 0);
syndrome : out STD_LOGIC_VECTOR (2 downto 0);
dataword : out STD_LOGIC_VECTOR (3 downto 0));
end sammy_2018314405;
architecture Behavioral of sammy_2018314405 is
signal s : std_logic_vector(2 downto 0);
signal b3, b2, b1, b0, q2, q1, q0 : std_logic;
signal temp : std_logic_vector(6 downto 0);
begin
b3 <= codeword(6);
b2 <= codeword(5);
b1 <= codeword(4);
b0 <= codeword(3);
q2 <= codeword(2);
q1 <= codeword(1);
q0 <= codeword(0);
s(0) <= b0 xor b1 xor b2 xor q0;
s(1) <= b1 xor b2 xor b3 xor q1;
s(2) <= b0 xor b1 xor b3 xor q2;
temp <= (b3,b2,b1,b0,q2,q1,q0);
--this part show error, can I put case in the middle of the code?
process(s)
begin
case s is
when "001" => temp(0) <= not temp(0);
when "010" => temp(1) <= not temp(1);
when "011" => temp(5) <= not temp(5);
when "100" => temp(2) <= not temp(2);
when "101" => temp(3) <= not temp(3);
when "110" => temp(6) <= not temp(6);
when "111" => temp(4) <= not temp(4);
when others => null;
end case;
end process;
syndrome(2 downto 0) <= s(2 downto 0);
dataword(3 downto 0) <= temp(6 downto 3);
end Behavioral;
Line 51: Net <temp[6]> is already driven by input port <codeword[6]>.
Net <temp[5]> is already driven by input port <codeword[5]>.
(This is code for 7 4 Hamming decoder.)
What should I do?
So far everything works as intended except for the Cout (carryout) and V (overflow) when I simulate in the testbench. I get constant Us when performing addition and subtraction. I performed some of the calculations I'm testing by hand so I know which should have a carry value and overflow value.
entity ALU is
Port ( Cin : in STD_LOGIC_VECTOR ( 0 downto 0);
ALUCntrl : in STD_LOGIC_VECTOR ( 3 downto 0);
A, B : in STD_LOGIC_VECTOR (31 downto 0);
ALUout : out STD_LOGIC_VECTOR (31 downto 0);
Cout, Z, V : out STD_LOGIC );
end ALU;
architecture Behavioral of ALU is
SIGNAL result : STD_LOGIC_VECTOR (32 downto 0);
SIGNAL bCout, bZ, bV : STD_LOGIC;
begin
WITH ALUCntrl SELECT
result(31 downto 0) <= A and B when "0000",
A or B when "0001",
A xor B when "0011",
std_logic_vector(unsigned(A) + unsigned(B) + unsigned(Cin)) WHEN "0010",
std_logic_vector(unsigned(A) - unsigned(B)) WHEN "0110",
A xnor B WHEN "1100",
A xnor B WHEN "1111",
"00000000000000000000000000000000" WHEN OTHERS;
WITH result(31 downto 0) SELECT
bZ <= '1' WHEN "00000000000000000000000000000000",
'0' WHEN OTHERS;
WITH ALUCntrl SELECT
bCout <= result(32) WHEN "0010",
result(32) WHEN "0110",
'0' WHEN OTHERS;
PROCESS(ALUCntrl)
BEGIN
CASE ALUCntrl IS
WHEN "0010" =>-- Addition Overflow
IF ((A(31) = '1') and (B(31) = '1') and (result(31) = '0')) THEN
bV <= '1';
ELSIF ((A(31) = '0') and (B(31) = '0') and (result(31) = '1')) THEN
bV <= '1';
ELSE
bV <= '0';
END IF;
WHEN "0110" => -- Subtraction overflow
IF ((A(31) = '0') and (B(31) ='1') and (result(31) = '1')) THEN
bV <= '1';
ELSIF ((A(31) = '1') and (B(31) = '0') and (result(31) = '0')) THEN
bV <= '1';
ELSE
bV <= '0';
END IF;
WHEN OTHERS =>
bV <= '0';
END CASE;
END PROCESS;
ALUout <= result(31 downto 0);
Cout <= bCout;
Z <= bZ;
V <= bV;
end Behavioral;
TEST-BENCH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALU_tb is
-- Port ( );
end ALU_tb;
architecture Behavioral of ALU_tb is
-- INPUTS
signal Cin : STD_LOGIC_VECTOR ( 0 downto 0);
signal A, B : STD_LOGIC_VECTOR (31 downto 0);
signal ALUCntrl : STD_LOGIC_VECTOR ( 3 downto 0);
-- OUTPUTS
signal ALUout : STD_LOGIC_VECTOR (31 downto 0);
signal Cout, Z, V : STD_LOGIC;
component ALU is
port(
Cin : in STD_LOGIC_VECTOR ( 0 downto 0);
A, B : in STD_LOGIC_VECTOR (31 downto 0);
ALUCntrl : in STD_LOGIC_VECTOR ( 3 downto 0);
ALUout : out STD_LOGIC_VECTOR (31 downto 0);
Cout, Z, V : out STD_LOGIC );
end component ALU;
begin
design_ALU: ALU
port map(
Cin => Cin,
A => A,
B => B,
ALUCntrl => ALUCntrl,
ALUout => ALUout,
Cout => Cout,
Z => Z,
V => V
);
tb : PROCESS
BEGIN
ALUCntrl <= "0000"; -- AND
Cin <= "00";
A <= "11111111111111111111111111111111";
B <= "00000000000000000000000000000000";
wait for 250ns;
ALUCntrl <= "0001"; -- OR
A <= "10011000100110001001100010011000";
B <= "10001001100010011000100110001001";
wait for 250ns;
ALUCntrl <= "0011"; -- XOR
A <= "00000001000000010000000100000001";
B <= "00010000000100000001000000010000";
wait for 250ns;
ALUCntrl <= "0010"; -- ADD
A <= "00000000000000000000000000000001";
B <= "11111111111111111111111111111111";
wait for 250ns;
ALUCntrl <= "0010"; -- ADD
A <= "01100011100010010111010101001111";
B <= "10101101010101100010010011100110";
wait for 250ns;
ALUCntrl <= "0010"; -- ADD
Cin <= "01";
A <= "00000000000000000000000000000001";
B <= "11111111111111111111111111111111";
wait for 250ns;
ALUCntrl <= "0010"; -- ADD
A <= "01100011100010010111010101001111";
B <= "10101101010101100010010011100110";
wait for 250ns;
ALUCntrl <= "0010"; -- ADD
A <= "11111111111111111111111111111111";
B <= "11111111111111111111111111111111";
wait for 250ns;
ALUCntrl <= "0110"; -- SUB
A <= "00000000000000000000000000000000";
B <= "00000000000000000000000000000001";
wait for 250ns;
ALUCntrl <= "0110"; -- SUB
A <= "11111001011010000100011110000011";
B <= "11111001100110001101010101100010";
wait for 250ns;
ALUCntrl <= "0110"; -- SUB
A <= "10000000000000000000000000000000";
B <= "00000001000000000000000000000000";
wait for 250ns;
ALUCntrl <= "1100"; -- NOR
A <= "10011010101111001101111011011111";
B <= "10011010101111001101111011111101";
wait for 250ns;
ALUCntrl <= "1111"; -- XNOR
A <= "10001001101111001101111000110100";
B <= "11000101001110111101011010000111";
wait;
END PROCESS tb;
end Behavioral;
This code works except for the add and subtract operations denoted by opcode 010 and 110 respectively. When I try to add the numbers the result looks as though a and b are being XOR'd and subtracting does A XNOR B. I have no idea why this is happening pls help. Also I am not allowed to use arithmetic plus or minus in my code the point of it is to add logically.
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
ENTITY Lab3ALU IS
PORT(
opcode :IN STD_LOGIC_VECTOR(2 DOWNTO 0);--INPUT
a :IN STD_LOGIC_VECTOR(31 DOWNTO 0);--INPUT
b :IN STD_LOGIC_VECTOR(31 DOWNTO 0);--INPUT
Cout :OUT STD_LOGIC;
Zero :OUT STD_LOGIC;
q :OUT STD_LOGIC_VECTOR(31 DOWNTO 0));--OUTPUT
END Lab3ALU;
ARCHITECTURE description of Lab3ALU IS
SIGNAL Reg1, Reg2, Reg3, Result : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL Cin, Sum, Carry : STD_LOGIC;
BEGIN
-- Update the register output on the clock's rising edge
process (a,b, opcode)
begin
Cin <= opcode(2);
Reg1 <= a;--temporarirly store A in Reg1 local variable
Reg2 <= b;--temporarily store B in Reg2 local variable
Reg3 <= NOT b;
case opcode is
When "000" => Result <= Reg1 AND Reg2;--AND
When "001" => Result <= Reg1 OR Reg2;--OR
When "010" =>
addloop: for i in 0 to 31 loop
Result(i) <= ((Reg1(i) XOR Reg2(i)) XOR Cin);
Cin <= (((Reg1(i) XOR Reg2(i))AND Cin)OR (Reg1(i) AND Reg2(i)));
end loop addloop;
When "110" =>
subloop: for i in 0 to 31 loop
Result(i) <= ((Reg1(i) XOR Reg3(i)) XOR Cin);
Cin <= (((Reg1(i) XOR Reg3(i))AND Cin)OR (Reg1(i) AND Reg3(i)));
end loop subloop;
When "100" => Result(31 downto 1) <= reg1(30 downto 0);
Result(0) <= '0';
Cin <= '0';
When "101" => Result(30 downto 0) <= reg1(31 downto 1);
Result(31) <= '0';
Cin <= '0';
When others => Result <= "00000000000000000000000000000000";
end case;
if Result = "00000000000000000000000000000000" then
Zero <= '1';
else
Zero <= '0';
end if;
q<= Result;
Cout<= Cin;
end process;
END description;```
I'm working on an ALU using a certain set of functions. I figured that the addition and bitshift portions would be a lot easier if I used an extra bit to store the carry out. I'm trying to concatenate an extra bit to two 8 bit long 'std_logic_vector's. The extra bit would hold the carry out in the addition.
However when I go to run the simulation after some debugging it doesn't look like the lines I used to give s_a and s_b their values are doing anything. If I were to take out the default values they come out empty.
I'm sure the error is something silly, I'm not to familiar with how concatenation works in vhdl, maybe theres a better way of storing the carry out, any help would be appreciated.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity ALU is
Port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
SEL : in std_logic_vector(3 downto 0);
Cin : in std_logic;
Result : out std_logic_vector(7 downto 0);
C : out std_logic;
Z : out std_logic);
end ALU;
architecture Behavioral of ALU is
signal s_result: unsigned(8 downto 0) := "000000000";
signal s_cin: unsigned(8 downto 0) := "000000000";
signal s_a: unsigned(8 downto 0) := "000000000";
signal s_b: unsigned(8 downto 0) := "000000000";
signal s_exempt: std_logic := '0';
begin
s1: process(A, B, SEL, CIN)
begin
s_a <= ('0' & unsigned(A));
s_b <= ('0' & unsigned(B));
s_cin(0) <= Cin;
s_exempt <= '0';
case SEL is
when "0000" =>
s_result <= s_a + s_b;
C <= s_result(8);
when "0001" => --ADDc Add with carry
s_result <= s_a + s_b + s_cin;
C <= s_result(8);
when "0010" => --SUB
if(s_a > s_b) then
s_result <= s_a - s_b;
C <= '0';
else
s_result <= s_b - s_a;
C <= '1';
end if;
when "0011" => --SUBc Subtract with carry
if(s_a > (s_b + s_cin)) then
s_result <= s_a - s_b - s_cin;
C <= '0';
else
s_result <= s_b - s_a - s_cin;
C <= '1';
end if;
when "0100" => --CMP Compare both values
if(s_a > s_b) then
C <= '0';
Z <= '0';
elsif(s_a = s_b) then
Z <= '1';
C <= '0';
else
C <= '1';
Z <= '1';
end if;
s_exempt <= '1';
when "0101" => --AND
s_result <= s_a AND s_b;
C <= '0';
when "0110" => Z<= '1'; --OR
s_result <= s_a OR s_b;
C <= '0';
when "0111" => --EXOR
s_result <= s_a XOR s_b;
C <= '0';
when "1000" => --TEST, comparator, flag change ONLY
if((s_a AND s_b) = "000000000")
then
C <= '0';
Z <= '1';
else
C <= '0';
Z <= '0';
end if;
when "1001" => --LSL Left shift
s_result <= s_a sll 1;
C <= s_result(8);
when "1010" => --LSR RIght shift
C <= s_a(0);
s_result <= s_a srl 1;
when "1011" => Z<= '1'; --ROL Rotate Left
s_result <= s_a sll 1;
C <= s_result(8);
s_result(0) <= s_result(8);
when "1100" => Z<= '1'; --ROR Rotate Right
C <= s_a(0);
s_result <= s_a srl 1;
s_result(0) <= s_a(0);
when "1101" => --ASR Arithemetic Roation
C <= s_a(0);
s_result <= s_a srl 1;
s_result(8) <= s_a(7);
when "1110" => --MOV Moves data into result
s_result <= s_b;
s_exempt <= '1';
when others =>
s_result <= "000000000";
s_exempt <= '1';
Z <= '0';
C <= '0';
end case;
if(s_exempt = '0') -- Checks Result for 0 if hasn't been found
then
if(s_result(7 downto 0) = "00000000")
then
Z <= '1';
else Z <= '0';
end if;
end if;
Result <= std_logic_vector(s_result(7 downto 0));
end process;
end Behavioral;
TESTBENCH:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity simulation is
end simulation;
architecture Behavioral of simulation is
COMPONENT ALU
Port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
SEL : in std_logic_vector(3 downto 0);
Cin : in std_logic;
Result : out std_logic_vector(7 downto 0);
C : out std_logic;
Z : out std_logic
);
END COMPONENT;
signal A : std_logic_vector(7 downto 0) := "00000000";
signal B : std_logic_vector(7 downto 0) := "00000000";
signal SEL : std_logic_vector(3 downto 0) := "0000";
signal Cin : std_logic;
signal Result : std_logic_vector(7 downto 0) := "00000000";
signal C: std_logic := '0';
signal Z: std_logic := '0';
begin
uut: ALU PORT MAP (
A => A,
B => B,
SEL => SEL,
Cin => Cin,
Result => Result,
C => C,
Z => Z
);
stim_proc: process
begin
A <= "00000001";
B <= "00100001";
SEL <= "0000";
Cin <= '1';
wait for 10ns;
wait;
end process;
end Behavioral;
Any signal assigned in a process in VHDL is not updated until the process suspends. So, for example, the value of s_result from this line:
s_result <= s_a + s_b + s_cin;
will not be updated by the time that this line is executed:
C <= s_result(8);
You need to find out about delta delays, then once you have, you will need to rewrite your code.
VHDL is a hardware description language. You are designing hardware, not writing software. For example, your initialisation of all your signals will not be implemented in hardware, meaning that your simulation may well behave differently to your hardware:
signal s_result: unsigned(8 downto 0) := "000000000";
signal s_cin: unsigned(8 downto 0) := "000000000";
signal s_a: unsigned(8 downto 0) := "000000000";
signal s_b: unsigned(8 downto 0) := "000000000";
signal s_exempt: std_logic := '0';