How to convert a SystemVerilog interface to individual ports - fpga

Question

I am looking into introducing interfaces into a code base that currently aren’t using interfaces.
For this I need to have adapters to turn the interface into individual signals again.
I was thinking of doing it like this:
interface foo();
logic a;
logic b;
logic c;
modport source(input a, c,
output b);
modport sink(input b, c,
output a);
endinterface // foo
module foo_source_to_ports
(
foo f,
input logic a,
input logic c,
output logic b);
assign f.a = a;
assign f.c = c;
assign b = f.b;
endmodule
module foo_ports_to_source
(
foo f,
output logic a,
output logic c,
input logic b);
assign a = f.a;
assign c = f.c;
assign f.b = b;
endmodule
module foo_sink_to_ports
(
foo f,
input logic b,
input logic c,
output logic a);
assign f.b = b;
assign f.c = c;
assign a = f.a;
endmodule
module foo_ports_to_sink
(
foo f,
output logic b,
output logic c,
input logic a);
assign b = f.b;
assign c = f.c;
assign f.a = a;
endmodule
I was wondering if someone knew of a better way of doing this. I guess I am not the only one with this problem.

Answer 1

I think you're overthinking it. Why don't you just instantiate your interface inside the RTL and connect its signals to the other signals directly using assign statements?
Even if you use an adapter that does these assigns for you you still have to specify all of the port connections for it at its instantiation, aside from the list of assigns that it contains. You'd have a lot of redundant information (hence a lot of places to edit in your code should changes be necessary).

Answer 2

This code looks very strange because:
The module port lists have both an interface and duplicate logic ports.
The interface ports do not have a modport indicating their role.
You're not showing how any of these modules would be instantiated and interconnected.
I know that vcs supports interface ports in the RTL, however mvsim does not.
This is what I would expect:
module source (
foo.source f
)
// Use interface
endmodule
module sink(
foo.sink f
);
module top();
foo f;
source u_source(.f(f));
sink u_sink(.f(f));
endmodule
Personally, I think that this is a terrific way to write the RTL and makes for much cleaner, more maintainable code. However, EDA support seems to be spotty.