Convertidor Binary to BCD - vhdl

Question

Because not store in BCD1 num_bin me ? This would correct syntax ?
Functional description
The operation must be as follows:
An activation of the reset will reset all internal registers , and pending the start circuit
a conversion. It will also put an end to '0'.
When you start = ' 1' conversion starts . The first step is to store the value there
in num_bin in an internal register .
Later will scroll the bits of this register on a second record
contain the number in BCD format ( in our case, as we have four digit registration It is 16 bits). The operation is synchronous with the rising edge of the clock.
Code:
entity bin2bcd is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
inicio : in STD_LOGIC;
num_bin : in STD_LOGIC_VECTOR (12 downto 0);
und : out STD_LOGIC_VECTOR (3 downto 0);
dec : out STD_LOGIC_VECTOR (3 downto 0);
cen : out STD_LOGIC_VECTOR (3 downto 0);
mil : out STD_LOGIC_VECTOR (3 downto 0);
fin : out STD_LOGIC);
end bin2bcd;
architecture Behavioral of bin2bcd is
signal bcd1: std_logic_vector (12 downto 0);
signal bcd2: std_logic_vector (15 downto 0);
begin
P1: process(reset,clk)
begin
if reset = '1' then
--fin <= '0';
bcd1 <= (others => '0'); -- registres to 0
bcd2 <= (others => '0'); -- registres to 0
elsif rising_edge(clk) then
if inicio = '1' then
bcd1 <= num_bin;
if bcd2(3 downto 0) > "0100" then -- if >4
bcd2(3 downto 0) <= bcd2(3 downto 0) or "0011";
end if;
if bcd2(7 downto 4) > "0100" then -- if >4
bcd2(7 downto 4) <= bcd2(7 downto 4) or "0011";
end if;
if bcd2(11 downto 8) > "100" then -- if >4
bcd2(11 downto 8) <= bcd2(11 downto 8) or "0011";
end if;
if bcd2(15 downto 12) > "0100" then -- if >4
bcd2(15 downto 12) <= bcd2(15 downto 12) or "0011";
end if;
for i in 0 to 12 loop
bcd2 <= bcd2(14 downto 0) & num_bin(12);
bcd1 <= bcd1(11 downto 0) & '0';
--fin <= '1';
end loop;
und <= bcd2 (3 downto 0); -- unidades
dec <= bcd2 (7 downto 4); -- decenas
cen <= bcd2 (11 downto 8); -- centenas
mil <= bcd2 (15 downto 12); -- millares
end if;
end if;
end process P1;
end Behavioral;

Answer 1

The problem I have is when you pretend to test_bench me num_bin value is not stored in bcd1 and also makes me very well the conversion and save it in bcd2

Answer 2

The problem is your for-loop, combined with the fact that you're assigning bcd1 earlier in the process. You seem to be intending to create a shift register, but that's not what the code you wrote actually does.
In VHDL, signals assigned in processes do not change value immediately - the assignment is scheduled for the end of the process (or any wait, in processes that have wait statements, though these are non-synthesizable).
Because of this, if your process "executes" multiple assignments to the same signal in the same process, later assignments override earlier assignments, and only the last assignment is what actually takes effect. So, since you have:
bcd1 <= num_bin;
...
for i in 0 to 12 loop
bcd2 <= bcd2(14 downto 0) & num_bin(12);
bcd1 <= bcd1(11 downto 0) & '0';
end loop;
the initial assignment will be overridden by the assignments in the for-loop, so you're never loading bcd1 with any value.
You also have a second problem, which is that your for-loop won't shift the register as you intend. A for-loop in a clocked process gets unrolled for every execution of the process, so this:
for i in 0 to 12 loop
bcd1 <= bcd1(11 downto 0) & '0';
end loop;
is equivalent to:
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
bcd1 <= bcd1(11 downto 0) & '0';
But, as I said before, since only the last assignment is the one that affects the signal, you're just shifting it once.
You probably meant to do:
if inicio = '1' then
bcd1 <= num_bin;
else
-- rest of your code goes here
That else is required so that the initial loading of bcd1 is not overridden by the later logic. You also need to fix your for-loop. Your algorithm may have multiple other problems, but this is the first one you need to deal with.