Can I pass a clock signal as an input argument in a Verilog task? - arguments

Question

I was writing a testbench in VCS(G-2012.09) to verify an SPI module.
Here is a task to get a byte from a SPI master:
task get_byte;
begin
repeat(8) #(posedge spck)
begin
if (spss == 1'b0)
tmp = {tmp[6:0], mosi};
end
$display ("[Time:%dns]---->Get a byte: 0x%h", $stime, tmp);
end
endtask
It works. Then I want to parameterize this task and replace the code with:
task get_byte;
input clk, oen, din;
output [7:0] byte;
begin
byte = 8'd0;
repeat(8) #(posedge clk)
begin
if (oen == 1'b0)
byte = {byte[6:0], din};
end
$display ("[Time:%dns]---->Get a byte: 0x%h", $stime, byte);
end
endtask
But when I called the task with get_byte(spck, spss, mosi, tmp) and run the testbench in VCS, it stucked. It seemed that spck did not pass to work as clk inside this task.
So is there a rule that a clock signal can not be used as an input argument within a task or did I make anything wrong?

Answer 1

In one of the old stackoverflow questions you can find following answer:
In Verilog arguments are passed to tasks by value. This means that the value of clock will be fixed for the lifetime of the call to the task. Your task will never find a posedge of clock, and will wait forever.
So the answer is: you can use clk as an input argument to a task, but it won't work as "standard" clock.

Answer 2

You can do what you ask if you declare the task as automatic and pass the input by reference (using the ref keyword instead of the input keyword in the port definition of the task)

Answer 3

Use the clock without declaring it an input, as you did in the first task. Passing by reference won't work either, since the task will try to set the clock signal at the end of the task, and the simulator will throw an error.
You may want to have several tasks that reference the different clk names, i.e.:
get_byte_spclk(...)
get_byte_clk(...)

Answer 4

As mentioned by Qiu, this will not work.
You however can do one trick.
see the code below:
task my_task;
#(posedge testbench.name_of_the_signal_you_want_to_use_as_refernce)
Do something here
endtask
So you basically have to give path to the clock signal, something like that:
testbech.instance_of_instantiated_module.clock_signal_name