I am working on an IR Decoder in VHDL and I know that the widths of an IR 1 bit is 1.2 ms, an IR 0 bit is 0.6 ms, and the start bit is 2.5 ms. I am trying to make a counter that takes in the 50MHz clock and converts to tenths of a millisecond. How can I do this?
entity counter is
Port ( EN : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR (4 downto 0));
end counter;
architecture Behavioral of counter is
constant max_count : integer := (2);
begin
startCounter: process(EN, RESET, CLK)
variable cnt : integer := 0;
variable div_cnt : integer := 0;
begin
if (RESET = '1') then
cnt := 0;
div_cnt := 0;
elsif (EN = '1' and rising_edge(CLK)) then
if (cnt = max_count) then
cnt := 0;
div_cnt:= div_cnt + 1;
else
cnt := cnt + 1;
end if;
end if;
COUNT <= conv_std_logic_vector(cnt, 5);
-- COUNT <= temp_count(16 downto 13);
end process startCounter;
end Behavioral;
Since you have a 50 MHz clock and want to generate a 0.1 msec pulse, you can use the ieee library, math_real, to compute the number of 50 MHz clocks to create a 0.1 msec pulse. Here's a code fragment.
library ieee;
use ieee.math_real.all;
-- omitting for clarity...
-- generate one clk cycle pulse with period of 0.1 msec
gen_0p1mspulse_p : process(Clk)
constant CLK_PERIOD : real := 1/50e6;
constant PULSE_PERIOD : real := 0.1e-3;
constant MAX_CNT : integer := INTEGER(PULSE_PERIOD/CLK_PERIOD);
variable cnt : integer range 0 to MAX_CNT-1 := 0;
begin
if rising_edge(Clk) then
if reset = '1' then
cnt := 0;
pulse_0p1msec <= '0';
else
pulse_0p1msec <= '0'; -- default value
if cnt < MAX_CNT-1 then
cnt := cnt + 1;
else
cnt := 0;
pulse_0p1msec <= '1';
end if;
end if;
end if;
end process;
-- logic using 0.1 msec pulse
your_logic_p : process(Clk)
begin
if rising_edge(Clk) then
if reset = '1' then
your_cnt := 0;
else
if pulse_0p1msec = '1' then
-- insert your logic here
end if;
end if;
end if;
end process;
I like to split up my VHDL processes so that they're short. I also prefer to use synchronous resets and enables since they synthesize to less hardware for Xilinx FPGAs as well as running at a higher clock rates. Hope that addresses your issue.
Related
I was wondering if someone could help me to find the error I am making when reading the analog input introduced to the AD7822 converter by a potentiometer capable of varying its voltage in a range of 0 to 5V.
As far as I understand what I have to do is to generate a 20ns wide pulse for the CONVST bit every 10MHz at most (starting from a clock operating at a maximum frequency of 50 MHz), then wait for the DR to be set to 0 and the value of the digital inputs could be taken.
Timeline for working with AD7822 in automatic mode
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity db_read is
generic
(
div : natural := 5
);
port
(
-- Input ports
clk_in : in std_logic;
rd : in std_logic;
db_input : in std_logic_vector (7 downto 0) := (others => '0');
-- Output ports
convst : out std_logic := '1';
db_output : out std_logic_vector (7 downto 0) := (others => '0')
);
end db_read;
-- Library Clause(s) (optional)
-- Use Clause(s) (optional)
architecture arch1 of db_read is
begin
----------------------------------------------------------------------
-- Send CONVST each div/50MHz ms.
----------------------------------------------------------------------
process(clk_in)
variable cont_convst : integer range 0 to div := 0;
begin
if (rising_edge(clk_in)) then
cont_convst := cont_convst + 1;
if (cont_convst = 1) then
convst <= '0';
else
convst <= '1';
end if;
if (cont_convst = div) then
cont_convst := 0;
end if;
end if;
end process;
----------------------------------------------------------------------
-- Read digital inputs when ready
----------------------------------------------------------------------
process(clk_in)
variable cont_rd : integer := 0;
begin
if (rising_edge(clk_in)) then
-- Detect if RD takes '0' value
if (rd = '0') then
cont_rd := cont_rd + 1;
end if;
if (cont_rd = 1) then
db_output <= db_input;
end if;
if (rd = '1') then
cont_rd := 0;
end if;
end if;
end process;
end arch1;
When I simulate it on a board what I see is that I always have all the outputs at high state regardless of the voltage that I introduce to the input of the converter.
I want to make a UART receiver that reads 8 consecutives bits with a parity bit at the end and with a simple stop bit. My FPGA have a clock of 100Mhz and the data that are transmitted to the uart have a rate of 56700 bauds. The dividing factor is 1736 (56700 * 1736 ≈ 100Mhz). The two outputs are the message of the input decoded by the uart and an error signal that indicates if the uart have correctly read the input. This is what I have :
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity uart_receiver is
generic (
clksPerBit : integer := 1736 -- Needs to be set correctly
);
port (
clk : in std_logic;
clk_en_uart : in std_logic ;
reset : in std_logic;
uart_rx : in std_logic;
error : out std_logic;
char : out std_logic_vector(7 downto 0)
);
end uart_receiver;
architecture uart_receiver_arch of uart_receiver is
type etat is (init, start_bit, receiving_bits, parity_bit,
stop_bit );
signal current_state : etat := init ;
signal error_signal : std_logic := '0';
signal clk_count : integer range 0 to clksPerBit-1 := 0;
signal bit_index : integer range 0 to 7 := 0; -- 8 Bits Total
signal data_byte : std_logic_vector(7 downto 0) := (others => '0');
begin
process (clk_en_uart)
begin
if rising_edge(clk_en_uart) then
end if;
end process;
process (clk,reset)
variable check_parity : integer range 0 to 7 := 0;
begin
if (reset = '1') then
current_state <= init;
error_signal <= '0';
clk_count <= 0;
bit_index <= 0;
data_byte <= (others => '0');
elsif rising_edge(clk) then
case current_state is
when init =>
clk_count <= 0;
Bit_Index <= 0;
if uart_rx = '0' then -- Start bit detected
current_state <= start_bit;
else
current_state <= init;
end if;
when start_bit =>
if clk_count = (clksPerBit-1)/2 then
if uart_rx = '0' then
clk_count <= 0; -- reset counter since we found the middle
current_state <= receiving_bits;
else
current_state <= init;
end if;
else
clk_count <= clk_count + 1;
current_state <= start_bit;
end if;
when receiving_bits =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= receiving_bits;
else
clk_count <= 0;
data_byte(bit_index) <= uart_rx;
if bit_index < 7 then
bit_index <= bit_index + 1;
current_state <= receiving_bits ;
else
bit_index <= 0;
current_state <= parity_bit;
end if;
end if;
when parity_bit =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= parity_bit;
else
for k in 0 to 7 loop
if ( data_byte(k) = '1' ) then
check_parity := check_parity + 1 ;
end if;
end loop;
if((uart_rx = '1' and check_parity mod 2 = 0) or (uart_rx = '0' and check_parity mod 2 = 1)) then
error_signal <= '1' ;
else
error_signal <= '0';
end if ;
current_state <= stop_bit;
end if;
when stop_bit =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= stop_bit ;
else
clk_count <= 0;
current_state <= init;
end if;
when others =>
current_state <= init;
end case;
end if;
char <= data_byte ;
error <= error_signal ;
end process;
end uart_receiver_arch;
So there's a phase shift between the data that is transmitted to the uart and his clock. If there's a phase shift, I'm not reading the data at the right time. I think that this code is sufficient to solve this problem. But, I've created a clock_divider and I can't seem to find a way to use it in this code. This is my clock divider :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divider is
generic (divfactor : positive := 1736);
Port (clk,clk2, reset : in STD_LOGIC ;
clkdiv, activationsig : out STD_LOGIC );
end clock_divider;
architecture clock_divider_arch of clock_divider is
begin
process(clk,reset)
variable clksigv : std_logic := '0' ;
variable activationsigv : std_logic := '0' ;
variable count : integer := 0 ;
begin
if (reset = '1') then
clksigv := '0' ;
activationsigv := '0' ;
count := 0 ;
elsif ( rising_edge(clk) ) then
count := count + 2 ;
if (activationsigv = '1') then
activationsigv := '0';
end if;
if ( count >= divfactor - 1 ) then
clksigv := not(clksigv) ;
if ( clksigv = '1' ) then
activationsigv := '1' ;
end if;
count := 0 ;
end if ;
end if ;
clkdiv <= clksigv ;
activationsig <= activationsigv;
end process ;
end clock_divider_arch;
The outputs of this clock divider are the clock divided and the activation signal that, when it is at '1', I have to read the data in the uart. So, the two outputs should also be inputs of the uart. In the uart_recevier, clk_en_uart is actually the clock divided, but I'm not using it because I don't know how.
I think that the solution is to 'activate' this divided clock when I enter in the start_bit case so that I have two clocks with the same phase and the same frequency, but I also think that it impossible to set a phase for a clock.
I'm not sure that I've clearly adressed my problem. If there's something that you don't understand in my code or in my explanation, feel free to ask questions.
Thank you for your help, hoping that I find a solution.
Sounds like the suggested solution is complicated for this problem.
A usual approach is that the receiver justs look for the falling edge of the start bit, then count for half a bit time (1736 / 2 cycles in your case), then samples the start bit value there, and subsequently samples the data, parity and stop bit values after each full bit time (1736 cycles in your case). After that start over looking for a new falling edge of the start bit.
The difference between the transmitter and receiver frequencies are then (usually) so small that the sample time will be practically in the middle for messages of only 11 bits at relative low bitrate, and the counter restart at falling edge of start bit ensures that any effect of long time frequency difference is removed.
As a learning exercise I am doing some HDMI experiments on an FPGA using VHDL. When coming to implement it in Vivado (2017.1) I am encountering the following warning in the timing report:
There are 11 register/latch pins with no clock driven by root clock pin: Hsync_i_reg/Q (HIGH)
I have opened the implemented schematic and looked for the pin in question. It seems to be connected to the same clock that everything else is connected to (and those are not flagged in the timing report), so I am confused as to what the errors above are referring to. Here are some shots from the schematics:
Here is the VHDL code of the offending design:
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_gen is
generic (
ha: integer := 96; --hpulse
hb: integer := 144; --hpulse+hbp
hc: integer := 784; --hpulse+hbp+hactive
hd: integer := 800; --hpulse+hbp+hactive+hfp
va: integer := 2; --vpulse
vb: integer := 35; --vpulse+vbp
vc: integer := 515; --vpulse+vbp+vactive
vd: integer := 525 --vpulse+vbp+vactive+vfp
);
port (
clk25: in std_logic; --tmds clock (25mhz)
hsync: out std_logic; --horizontal sync
vsync: out std_logic; --vertical sync
hactive: out std_logic; --active portion of hsync
vactive: out std_logic; --active portion of vsync
dena: out std_logic --display enable
);
end entity;
architecture behavioral of ctrl_gen is
signal hsync_i, hactive_i, vactive_i, vsync_i : std_logic;
begin
-- horizontal signals generation
hproc : process (clk25)
variable hcount: integer range 0 to hd := 0;
begin
if rising_edge(clk25) then
hcount := hcount + 1;
if (hcount=ha) then
hsync_i <= '1';
elsif (hcount=hb) then
hactive_i <= '1';
elsif (hcount=hc) then
hactive_i <= '0';
elsif (hcount=hd) then
hsync_i <= '0';
hcount := 0;
end if;
end if;
end process;
-- vertical signals generation
vproc : process (hsync_i)
variable vcount: integer range 0 to vd := 0;
begin
if falling_edge(hsync_i) then
vcount := vcount + 1;
if (vcount=va) then
vsync_i <= '1';
elsif (vcount=vb) then
vactive_i <= '1';
elsif (vcount=vc) then
vactive_i <= '0';
elsif (vcount=vd) then
vsync_i <= '0';
vcount := 0;
end if;
end if;
end process;
dena <= hactive_i and vactive_i;
hsync <= hsync_i;
vactive <= vactive_i;
hactive <= hactive_i;
end behavioral;
On reflection, I think that the warning is telling me that Hsync_i_reg/Q is the clock used for the Vcount registers, not that Hsync_i_reg itself if not connected to the root clock pin?
Is the method I have used bad practice and unlikely to work? The overall design is not working and I'm trying to understand whether this is the cause.
Thanks.
I see potential design issues. First being the use of variable for objects that are actually clocked signals. Secondly, you're using a generated signal as a clock input. That's also not nice.
I would modify your code to the following (not tested if it completely does what your code did before)
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_gen is
generic (
ha: integer := 96; --hpulse
hb: integer := 144; --hpulse+hbp
hc: integer := 784; --hpulse+hbp+hactive
hd: integer := 800; --hpulse+hbp+hactive+hfp
va: integer := 2; --vpulse
vb: integer := 35; --vpulse+vbp
vc: integer := 515; --vpulse+vbp+vactive
vd: integer := 525 --vpulse+vbp+vactive+vfp
);
port (
clk25: in std_logic; --tmds clock (25mhz)
hsync: out std_logic; --horizontal sync
vsync: out std_logic; --vertical sync
hactive: out std_logic; --active portion of hsync
vactive: out std_logic; --active portion of vsync
dena: out std_logic --display enable
);
end entity;
architecture behavioral of ctrl_gen is
signal hsync_i, hactive_i, vactive_i, vsync_i : std_logic;
signal hcount: integer range 0 to hd-1 := 0;
signal vcount: integer range 0 to vd-1 := 0;
begin
-- horizontal signals generation
hproc : process (clk25)
begin
if rising_edge(clk25) then
if hcount < hd-1 then
hcount <= hcount + 1;
else
hcount <= 0;
end if;
if (hcount=ha-1) then
hsync <= '1';
end if;
if (hcount=hb-1) then
hactive_i <= '1';
end if;
if (hcount=hc-1) then
hactive_i <= '0';
end if;
if (hcount=hd-1) then
hsync <= '0';
end if;
end if;
end process;
-- vertical signals generation
vproc : process (clk25)
begin
if rising_edge(clk25) then
if hcount = hd-1 then -- moment of falling_edge hsync.
if vcount < vd-1 then
vcount <= vcount + 1;
else
vcount <= 0;
end if;
if (vcount=va-1) then
vsync <= '1';
end if;
if (vcount=vb-1) then
vactive_i <= '1';
end if;
if (vcount=vc-1) then
vactive_i <= '0';
end if;
if (vcount=vd-1) then
vsync <= '0';
end if;
end if;
end if;
end process;
dena <= hactive_i and vactive_i;
vactive <= vactive_i;
hactive <= hactive_i;
end behavioral;
I think:
signal hcount: integer range 0 to hd-1 := 0;
signal vcount: integer range 0 to vd-1 := 0;
Is not a valid synthesis type for hcount, vcount: it should be std_logic_vector
I have searched about this problem but it all seemed Greek to me so I came here as last effort.I have the following VHDL code that I want to be implemented on an fpga.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use work.conversions.all;
entity counter is
port ( clk_in: in std_logic; --new clock
target : in std_logic_vector(7 downto 1); --Set the target with the switches (SW7-SW1)
start : in std_logic; --Start/pause (SW0)
rst : in std_logic; --Reset (BT0)
LD : out std_logic_vector(7 downto 1); --Leds show the target at binary (LD7-LD1)
LD0 : out std_logic; --LD0 indicates thw the limit has been reached
seg : out std_logic_vector(7 downto 0); --7 segment display
digit : out std_logic_vector(3 downto 0)
);
end counter;
architecture Behavioral of counter is
begin
process(clk_in,target,rst)
variable timer : natural := 0;
variable counter : natural := 0;
variable display_counter : natural range 0 to 4 := 0;
begin
LD0 <= '0';
LD <= target; --Show the target at the leds
digit <= "1110"; --Last digit active
seg <= "00000011"; --Show zero
<--->if(rst='1') then --Reset counter
counter := 0;
timer := 0;
digit <= "1110"; --Last digit active
seg <= "00000011"; --Show zero
LD0 <= '0';
elsif rising_edge(clk_in) then
if(start = '0') then --Pause
--counter := counter;
elsif(counter = conv_integer(unsigned(target))) then --timer limit has been reached
LD0 <= '1';
else
counter := counter + 1;
display_counter := display_counter + 1;
if(counter rem 10 = 0) then --one second has elapsed (10Hz cycle)
timer := timer + 1; --increase timer
end if;
case display_counter is --Select which digits are gonna be activated and with what
when 1 =>
seg <= int2led(timer/1000);
if(int2led(timer/1000) = "00000000") then
digit(3) <= '1';
else
digit(3) <= '0';
end if;
when 2 =>
seg <= int2led((timer/100) mod 10);
if(int2led((timer/100) mod 10) = "00000000") then
digit(2) <= '1';
else
digit(2) <= '0';
end if;
when 3 =>
seg <= int2led((timer/10) mod 10);
if(int2led((timer/10) mod 10) = "00000000") then
digit(1) <= '1';
else
digit(1) <= '0';
end if;
when others =>
seg <= int2led(timer/10);
if(int2led(timer/10) = "00000000") then
digit(1) <= '1';
else
digit(1) <= '0';
end if;
end case;
if (display_counter = 4) then --reset the display counter from time to time
display_counter := 0;
else
display_counter := display_counter;
end if;
end if;
end if;
end process;
end Behavioral;
The problem is at if(rst='1') then. Can anyone explain to me in plain English why is this happening and a solution to it so I won't have the same kind problems again? Thanks in advance
You have default signal assignments before the if rst='1' then clause.
That means, when rst returns to 0 (in simulation) these default assignments will execute, and delete the reset values of those signals.
XST is telling you that the hardware can't actually do that.
The solution is to delete those default assignments, which will restore this process to a standard form. Then think carefully about what they were for and how to keep their functionality if you need to.
The traditional place for such assignments is immediately after the elsif rising_edge(clk) then clause, where they will be executed on every clock edge (provided Rst is low) then overridden by any other assignments that are executed yb the process.
I am using the following VHDL to take a 100 Mhz clock and put out a 25 Mhz clock. :
process(clk, reset)
variable count : integer range 0 to 2;
begin
if (reset = '1') then
clock_25MHz <= '0';
count := 0;
elsif rising_edge(clk) then
count := count+1;
if(count >= 2) then
clock_25MHz <= not clock_25MHz;
count := 0;
end if;
end if;
end process;
It is giving me this warning:
"WARNING:Xst:1293 - FF/Latch count_1 has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process."
I don't understand why its happening. Can anyone shed some light on this for me? Thanks!
You don't need 2 bits of count. A single flip flop is enough.
If you add an integer signal CNT that's assigned count (allowing me to see it on a waveform with ghdl):
library ieee;
use ieee.std_logic_1164.all;
entity clk_div is
end entity;
architecture foo of clk_div is
signal clk: std_logic := '0';
signal reset: std_logic := '1';
signal clock_25MHz: std_logic;
signal CNT: integer;
begin
CLKDIV:
process(clk,reset)
variable count: integer range 0 to 2;
begin
if (reset = '1') then
clock_25MHz <= '0';
count:=0;
elsif rising_edge(clk) then
count:=count+1;
if(count>=2) then
clock_25MHz <= not clock_25MHz;
count:=0;
end if;
end if;
CNT <= count;
end process;
CLOCK:
process
begin
wait for 5 ns;
clk <= not clk;
if Now > 200 ns then
wait;
end if;
end process;
UNRESET:
process
begin
wait for 20 ns;
reset <= '0';
wait;
end process;
end architecture;
You find:
The count always shows up as either 0 or 1 and not 2 or 3, because you assign it to 0 when ever its 2 or greater. It never shows up as 2 on a clock edge.
Is that correct? Why yes it is. If you clock at the waveform with clock_25MHz lasting 4 100 Mhz clocks it works perfectly. You're process is doing something that's not necessary, count doesn't need a range of 0 to 2, (requiring two flip flops).
Change the evaluation order for count so clock_25MHz is toggled when count = 1, then toggle count. Change the range of count to 0 to 1 or better still make it type std_logic.
-- signal CNT: integer;
signal toggle_ff: std_logic;
begin
CLKDIV:
process(clk,reset)
--variable count: integer range 0 to 2;
variable toggle: std_logic;
begin
if (reset = '1') then
clock_25MHz <= '0';
-- count:=0;
toggle := '0';
elsif rising_edge(clk) then
-- count:=count+1;
-- if(count>=2) then
if toggle = '1' then
clock_25MHz <= not clock_25MHz;
-- count:=0;
end if;
toggle := not toggle;
end if;
-- CNT <= count;
toggle_ff <= toggle;
end process;
Which gives:
You could also use a signal in the process statement instead of a variable. In my example code rename toggle_ff to toggle, remove the variable toggle declaration and remove the signal assignment statement to toggle_ff. The reason this will work seamlessly is because you evaluate the output of the toogle FF before it is toggled.
The warning occurs since the state in count implemented as FF/Latch by Xilinx
goes 0, 1, 0, 1, ..., and only an internal combinatorial value of count ever
gets the value 2, thus any bit 1 in the count state will always be 0, as the
warning says "FF/Latch count_1 has a constant value of 0 in block".
You can also see this since the code can be rewritten with reduced ´count´
range as 0 to 1, if the count increment is placed inside the if like:
process(clk, reset)
variable count : integer range 0 to 1;
begin
if (reset = '1') then
clock_25MHz <= '0';
count := 0;
elsif rising_edge(clk) then
if (count = 1) then
clock_25MHz <= not clock_25MHz;
count := 0;
else
count := count + 1;
end if;
end if;
end process;
But based on the specific requirement of doing a division by 4 from a 100 MHz
to a 25 MHz clock, it may be more obvious creating an intermediate 50 MHz clock
instead of count, with code like:
process(clk, reset)
variable clock_50MHz : std_logic;
begin
if (reset = '1') then
clock_25MHz <= '0';
clock_50MHz := '0';
elsif rising_edge(clk) then
clock_50MHz := not clock_50MHz;
if clock_50MHz = '1' then
clock_25MHz <= not clock_25MHz;
end if;
end if;
end process;