I'd like to know why constraint Errors warnings are prompted in Ada when enums are used as in the example below. As I've been using Enums I can replace them for a better implementation.
type Uart_Instance_Type is (COM1, COM2, COM3);
for Uart_Instance_Type use
( COM1 => 16#0001# ,
COM2 => 16#0002# ,
COM3 => 16#0003#
);
type UART_Register_Type is record
SR : Half_Word; -- USART Status register
Reserved_0 : Half_Word;
DR : Half_Word; -- USART Data register
Reserved_1 : Half_Word;
BRR : Half_Word; -- USART Baud rate register
Reserved_2 : Half_Word;
end record
with volatile;
for UART_Register_Type use record
SR at 0 range 0 .. 15;
Reserved_0 at 2 range 0 .. 15;
DR at 4 range 0 .. 15;
Reserved_1 at 6 range 0 .. 15;
BRR at 8 range 0 .. 15;
Reserved_2 at 10 range 0 .. 15;
end record;
type UART_Register_Access is access all UART_Register_Type;
UARTs: array (Uart_Instance_Type range COM1 .. COM3) of aliased UART_Register_Access;
The compiler prompt at the last line ("UARTs: ...) and shows:
warning: "Constraint Error" may call Last_Chance_Handler
Is there a better implementation to avoid these warnings when using Enums?
Thanks in advance! :)
I think you must be compiling for a restricted (Ravenscar?) runtime, which is why any exception will result in a call to Last_Chance_Handler.
I encountered a lot of irritating warnings like this, and eventually traced it to compiling with
-gnatwa (“turn on all info/warnings marked below with +”) which enables
-gnatw.x ("turn on warnings for non-local exception”).
You can suppress the warnings with -gnatw.X.
(For info, you can see the command line options by saying gnatmake -h (or arm-eabi-gnatmake -h). There are a lot.)
Related
I am currently working on a project that requires serial communication between PIC 24FV16KA302 and a PC software.
I have searched the Internet for the past 3 days and i cant find an answer for my problem so i decided to ask here . This is my first visual studio program so i dont have any experience with the software.
The PIC has few variables and two 8x16 tables that i need to view and modify on the PC side . The problem comes when i send the tables , all other information is received without a problem . I am using serial connection ( 38400/8-N-1 ) via uart to usb converter
FT232
When the PC send "AT+RTPM" to the PIC .
Button7.Click
SerialPort1.ReceivedBytesThreshold = 128
MachineState = MS.Receive_table
SerialPort1.Write("AT+RTPM")
End Sub
The PIC sends back 128 Bytes( the values in the table )
case read_table_pwm : // send pwm table
for (yy = 0 ; yy < 8 ; yy ++) {
for (xx = 0 ; xx < 16 ; xx++ ) {
uart_send_char(controll_by_pmw_map_lb[yy][xx]) ;
}
}
at_command = receive_state_idle ;
break ;
Which the software is suppose to get and display in a DataGrid.
Private Sub SerialPort1_DataReceived(sender As Object, e As IO.Ports.SerialDataReceivedEventArgs) Handles SerialPort1.DataReceived
If MachineState = MS.Receive_table Then
SerialPort1.Read(Buffer_array_received_data, 0, 128)
cellpos = 0
For grid_y As Int16 = 0 To 7 Step 1
For grid_x As Int16 = 0 To 15 Step 1
DataGridView1.Rows(grid_y).Cells(grid_x).Value = Buffer_array_received_data(cellpos)
cellpos += 1
Next
Next
End Sub
The problem is that most of the time ( 99 % ) it displays only part of the dataset and zeros to the end , and when i try to do it again it display the other part and it starts from the beginning .
First request
Second request
If i try the same thing with another program i always get the full dataset
Realterm
Termite
I have tried doing it cell by cell , but it only works if i request them one very second , other wise i get the same problem .
After that i need to use a timer ( 100 ms ) to request live data from the PIC .
this work better but still some of the time i get some random data. I haven't focused on that for the moment because without the dataset everything else is useless .
Am i missing something or has anyone encountered the same problem ?
I managed to solve the problem by replacing
SerialPort1.Read(Buffer_array_received_data, 0, 128)
with
For byte_pos As Int16 = 0 To 127 Step 1
Buffer_array_received_data(byte_pos) = SerialPort1.ReadByte()
Next
But aren't they supposed to be the same ?
I would like to use a simple test harness to test my code during debugging using the same methodology as the Forth test harness developed by John Hayes.
The concept is to define a function, say my+ and then to define simple code snippets that will test the code when Tdebug is on.
Tdebug if T{ 1 1 my+ -> 2 }T else
Is it really as simple as including tester.f and changing {> to T{ and } to }T?
I plan to omit tester.f in the production release if size is an issue.
Edit:
debug if ... then does not work because it is outside compile...
Now I need help!
If debug is true tester.f works well.
If debug is false t{ and }t must work like ( ... ) comments. How do I code this?
0 constant debug
: t{
debug if
( as defined in tester.fr )
else
( what goes here? )
then
;
: }t
debug if
( as defined in tester.fr )
else
( and what goes here? )
then
;
The only way is to parse the input source stream up to }t. If t{ can be nested, it becomes a little trickier — see the reference implementation of [ELSE] word.
For reference, the production-mode definition of t{ word for simple (not nested) case in standard Forth:
: t{ ( "ccc }t" -- ) \ skip up to '}t'
begin
begin parse-name dup while S" }t" compare 0= until exit then 2drop
refill 0=
until
;
Although, I suggest to place tests into separate files and make conditional inclusion of such files ("spec" files). In such case you don't need to have another (production-mode) definition of t{ word at all.
I eventually did something similar to #ruvim by including tester.f when in debug mode and including notester.f when in production as follows:
\ notester.fs
( include either tester.fs or notester.fs )
\ adapted from longcomment.txt
false variable verbose
: t{ ( -- ) \ Long comment
begin
token \ Get next token
dup 0= if 2drop cr query token then \ If length of token is zero, end of
\ line is reached.
\ Fetch new line. Fetch new token.
s" }t" compare \ Search for }t
until
immediate 0-foldable
;
: testing ( -- ) \ Talking comment.
source verbose #
if dup >r type cr r> >in !
else >in ! drop [char] * emit
then
;
t{ 1 1 + -> 2 }t \ Usage sample
I find that having the tests as usage comments in the production file assists clarity.
My program should allow the user to choose ice cream from menu then add the price for the ice cream to show total price of the ice cream.However my output for total price is wrong. For example if i choose 1 and 2 the answer should be 1.5+1.7=3.2 but I get 3.4. Also if i choose 2 I'll only get error. Please help me.
program iceCream;
var
count,i: integer;
price:array[1..50]of real;
totalPrice: real;
choice: integer;
begin
count:= 0;
writeln ( ' ICE CREAM FLAVOUR');
write ( ' 1.Vanilla: RM 1.50 | 3.Chocolate: RM 2.00');
writeln;
write ( ' 2. Strawberry: RM 1.70 | 0. Exit ');
writeln;
repeat
write ( ' Enter your choice(number): ');
readln ( choice);
if choice <= 3 then
count:= count+1
else
writeln ( 'Invalid choice');
case choice of
1: begin
price[i]:= 1.50;
end;
2: begin
price[i]:= 1.70 ;
end;
3: begin
price[i]:= 2.00;
end;
end;
for i:= 1 to count do
begin
totalPrice:= totalPrice+price[i];
end;
until choice = 0;
writeln ( ' Total ice-cream: ', count);
readln;
writeln ( ' Total price: RM ', totalPrice:2:2);
readln;
end.
I won't answer your question here. It's more important to find out what you're doing wrong and how you can solve the problem on your own.
How to find out what's going wrong?
The compiler shows two warnings when it compiles your code:
Warnings: 2
project1.lpr(29,17) Warning: Variable "i" does not seem to be initialized
project1.lpr(44,25) Warning: Variable "totalPrice" does not seem to be initialized
This kind of warnings appears when you read a variable without having a value assigned to it. The compiler leads you to the location of the unsafe code. The first warning is located in line 29 in column 17:
1: begin
price[i]:= 1.50; // i has not been set before. So its value is undefined or 0
end;
Is your intention to use set Price[i] here? So why hasn't it been assigned to a value before?
Or do you have a different variable that holds the number of ice creams? Why don't you use that?
Let's take a look at the second warning in line 44 in column 25. It's this line:
totalPrice:= totalPrice+price[i];
// ^
Are you sure totalPrice has been initialized correctly?
Even though you initialize it correctly the program may still doesn't work properly. In that case it helps to debug the application.
Open your application in the Lazarus IDE and press F8 to step through your program. You go from line to during the execution of your program. You will see what's wrong then.
My goal is to write a string to a file where the size of the string will vary. At the moment I have made the string very large so that there is no overflow but is there a way to make it so that the size of the string is the exact number of characters I'm placing into it? I've tried something like the code below but it gives me an error unknown identifier "address count" I think it is because address count is a variable declared in a process and address count is constantly changing. Is there any way around this?
signal address_map :string (1 to address_count);
many thanks
leo
"My goal is to write a string to a file." Hence, lets just focus on that.
Step 1: reference the file IO packages (recommended to turn on VHDL-2008):
use std.textio.all ;
-- use ieee.std_logic_textio.all ; -- include if not using VHDL-2008
Step 2: Declare your file
file MyFile : TEXT open WRITE_MODE is "MyFile.txt";
Step 3: Create a buffer:
TestProc : process
variable WriteBuf : line ;
begin
write ... -- see step 4
writeline ... -- see step 5
Step 4: Use write to write into the buffer (in the process TestProc):
write(WriteBuf, string'("State = ") ) ; -- Any VHDL version
write(WriteBuf, StateType'image(State)) ;
swrite(WriteBuf, " at time = " ); -- VHDL-2008 simplification
write(WriteBuf, NOW, RIGHT, 12) ;
Step 5: Write the buffer to the file (in the process TestProc):
writeline(MyFile, WriteBuf) ;
Alternate Steps 3-5: Use built-in VHDL Write with to_string:
Write(MyFile, "State = " & to_string(State) &
", Data = " & to_hstring(Data) &
" at time " & to_string(NOW, 1 ns) ) ;
Alternate Steps 1-5: Use OSVVM (see http://osvvm.org) (requires VHDL-2008):
library osvvm ;
use osvvm.transcriptpkg.all ; -- all printing goes to same file
. . .
TestProc : process
begin
TranscriptOpen("./results/test1.txt") ;
Print("State = " & to_string(State) &
", Data = " & to_hstring(Data) &
" at time " & to_string(NOW, 1 ns) ) ;
One hard but flexible solution is to use dynamic allocation features of VHDL (copied from ADA).
You have to use an access of string (it is roughly like a "pointer to a string" in C)
type line is access string;
you event don't have to do it because line is already declared in std.textio package.
Ok, the problem next is that you can't use an access type for a signal, so you have to use a shared variable:
shared variable address_map: line;
And finally you have to allocate, read and write to this line:
--Example in a function/procedure/process:
--free a previously allocated string:
if address_map /= NULL then
deallocate(address_map);
end if;
--allocate a new string:
address_map:=new string (1 to address_count);
address_map(1 to 3):="xyz";
--we have here:
-- address_map(1)='y'
-- address_map(2 to 3)="yz"
-- address_map.all = "xyz"
Notice the use of new/deallocate (like malloc/free in C or free/delete in C++).
It is not easy to handle this kind of code, I recommend you to read the documentation of VHDL keywords "new", "deallocate" and "access" (easily found with your favorite search engine) or feel free to ask more questions.
You can also use the READ (read the whole line into a string) and WRITE (append a string to the line) functions from std.textio package.
I'm using ISE 14.7 and i'm trying to create design with some 1-bit-wide distributed RAM blocks.
My memory declaration:
type tyMemory is array (0 to MEMORY_NUM - 1) of std_logic_vector(MEMORY_SIZE - 1 downto 0) ;
signal Memory: tyMemory := ( others => (others => '0')) ;
attribute ram_style : string ;
attribute ram_style of Memory : signal is "distributed" ;
My code:
MemoryGen : for i in 0 to MEMORY_NUM - 1 generate
process( CLK )
begin
if rising_edge(CLK) then
if CE = '1' then
DataOut(i) <= Memory(i)(Addr(i)) ;
Memory(i)(Addr(i)) <= DataIn(i) ;
end if ;
end if ;
end process ;
end generate ;
After synthesis i get this warning:
WARNING:Xst:3012 - Available block RAM resources offer a maximum of two write ports.
You are apparently describing a RAM with 16 separate write ports for signal <Memory>.
The RAM will be expanded on registers.
How can i forse xst to use distributed memory blocks with size=ARRAY_LENGTH and width=1?
I can create and use separate memory component(and is works), but i need more elegant solution.
You need to create an entity that describes a variable length 1-bit wide memory, then use a generate statement to create an array of these. While what you have done would provide the functionality you are asking for in a simulator, most FPGA tools will only extract memory elements if your code is written in certain ways.
You can find documentation on what code Xilinx ISE tools will understand as a memory element by selecting the appropriate document for your device here http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ise_n_xst_user_guide_v6s6.htm . Look under 'HDL Coding techniques'.
Note that if your memory length is large, you will not be able to get maximum performance from it without adding manual pipelining. I think you will get a synthesis message if your memory exceeds the intended useful maximum length for distributed memories. Assuming you are using a Spartan 6 device, you can find information on what the useful supported distributed memory sizes are here: http://www.xilinx.com/support/documentation/user_guides/ug384.pdf page 52.
This should inferre 16 one bit wide BlockRAMs:
architecture ...
attribute ram_style : string;
subtype tyMemory is std_logic_vector(MEMORY_SIZE - 1 downto 0) ;
begin
genMem : for i in 0 to MEMORY_NUM - 1 generate
signal Memory : tyMemory := (others => '0');
attribute ram_style of Memory : signal is "block";
begin
process(clk)
begin
if rising_edge(clk) then
if CE = '1' then
Memory(Addr(i)) <= DataIn(i) ;
DataOut(i) <= Memory(Addr(i)) ;
end if ;
end if ;
end process ;
end generate ;
end architecture;