Arrays as buffer VHDL - vhdl

Question

I need to create a FIFO buffer in VHDL. I need to use a 2 dimensional array to storage data like (number of data)(n-bit data).
If I create a single "big" array that storage for example 1000 entrys. Every new data clock I storage one slot. And every output data clock I output a data. What happen if this two clocks occour near at the same time?
For example:
if rising_edge(INPUT_DATA) then
Register_Array(Counter_IN) <= DataIN;
Counter_IN <= Counter_IN + 1;
end if;
if rising_edge(OUTPUT_DATA) then
DataOUT <= Register_Array(Counter_OUT);
Counter_OUT <= Counter_OUT + 1;
end if;
If it's possible to create a process like this, what happen if two clock are near at the same time?
Consider I can't lose any data.

Answer 1

What you are asking about here is a clock domain crossing FIFO, or CDC FIFO.
Clock domain crossing FIFOs are surprisingly difficult to design. There are many pitfalls, and most of them cannot be checked by simulation.
As for your arrays, you should use arrays of std_logic_vector, like in the answer linked to by #Nicolas Roudel.
But this is still far from a functioning CDC FIFO. You also need read and write pointers in gray format, gray to bin pointer conversion, clock domain crossings for the two gray pointers, empty and full indications, read and write signals, proper attributes to prevent the synthesizer from breaking the clock domain crossings, and timing constraints.
All this is needed to properly protect against exactly the thing you ask about: "What happens when two clocks occur at almost the same time?"
The thing that happens when two clocks occur at almost the same time is called "metastability", and it will cause all kinds of bad and unpredictable things in your design.
If you get only one thing in the design of the CDC FIFO wrong, your design will likely work fine in simulation, and even in hardware. Most of the time........ :-)
All FPGA vendors have ready-made CDC FIFOs which you can use. I would highly recommend that beginners consider using the ready-made FIFOs for production designs.
But at the same time, designing a CDC FIFOa is a nice challenge to learn about clock domain crossings and metastablity.
This is one of many pages where you can find information about how to handle clock domain crossings: https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html
There is also a related stackexchange answer here: https://electronics.stackexchange.com/questions/97280/trying-to-understand-fifo-in-hardware-context