FIFO one clock Head and Tail error - VHDL - vhdl

Question

After some advice on this site I've decided to use one clock FIFO. I've simulated it without errors before synthesizing it, after synthesize I've simulated code and I get this error:
** Warning: Read and Write to same address at same time. RD is unpredictable, driving RD to X
Time: 200877700 ps Iteration: 1 Instance: /testbench/FIFO/memory_tile_I_1
But simulations works like expected. After compiling I simulated again the code and I didn't get this error and simulation worked like expected.
My code is:
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity FIFO is
Generic (
constant DATA_WIDTH : positive := 8;
constant FIFO_DEPTH : positive := 500
);
Port (
Clock : in STD_LOGIC;
WriteEn : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
ReadEn : in STD_LOGIC;
DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
Empty : out STD_LOGIC;
Full : out STD_LOGIC;
ModuleRESET : in STD_LOGIC
);
end FIFO;
architecture FIFO_archi of FIFO is
type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
signal Memory : FIFO_Memory;
signal Head : natural range 0 to FIFO_DEPTH - 1;
signal Tail : natural range 0 to FIFO_DEPTH - 1;
begin
-- Memory Pointer Process
process (Clock, ModuleRESET)
variable Looped : boolean;
begin
if ModuleRESET = '0' then
Head <= 0;
Tail <= 0;
Looped := false;
Full <= '0';
Empty <= '1';
DataOut <= (others => '0');
elsif rising_edge(Clock) then
if ReadEn = '1' then
if ((Looped = true) or (Head /= Tail)) then
-- Update data output
DataOut <= Memory(Tail);
-- Update Tail pointer as needed
if (Tail = FIFO_DEPTH - 1) then
Tail <= 0;
Looped := false;
else
Tail <= Tail + 1;
end if;
end if;
elsif WriteEn = '1' then
if ((Looped = false) or (Head /= Tail)) then
-- Write Data to Memory
Memory(Head) <= DataIn;
-- Increment Head pointer as needed
if (Head = FIFO_DEPTH - 1) then
Head <= 0;
Looped := true;
else
Head <= Head + 1;
end if;
end if;
end if;
-- Update Empty and Full flags
if (Head = Tail) then
if Looped then
Full <= '1';
else
Empty <= '1';
end if;
else
Empty <= '0';
Full <= '0';
end if;
end if;
end process;
end FIFO_archi;
I get this error every time I write the first data in simulation after synthesize(with synplify pro):
When I initialize the code and write first data
Every time I empty FIFO buffer and write first data
Of course I have Tail and Head at position 0 when my buffer is empty, but since I have two flags with an if-elseif istance, how it's possible I get an error on Read and Write same address?