I'm writing a computational pipeline for some processing of neuroimaging data with make.
I chose to use make for this task for the advantages that it provides as incrementality, dependency management and easy parallelization of tasks (the latter two are my main focus).
I started writing the Makefile for a single subject and it worked correctly. Now I tried to extend it to perform the same tasks for all the subjects, but I got stuck on the commented part of the Makefile shown below.
File organization is like this:
aal/
data
subj1/
dti/
data
t1/
data
subj2/
dti/
data
t1/
data
subj3/
dti/
data
t1/
data
and this is what I currently got
LOGOPT := >> log.txt 2>> log.txt
SUBJS := subj1 subj2 subj3
MNI_ROIS := ${wildcard AAL/AAL_to_MNI_*.nii.gz}
DIFF_ROIS := ${subst AAL/AAL_to_MNI_,DTI/aal2diff/AAL_,$(MNI_ROIS)}
all: $(SUBJS)
$(SUBJS): % : %/transf/MNI_to_T1_warp.nii.gz %/transf/T1_to_DTI.mat ${addprefix %/,$(DIFF_ROIS)}
#DTI/aal2diff/AAL_%.nii.gz: AAL/AAL_to_MNI_%.nii.gz DTI/nodif_brain.nii.gz transf/MNI_to_T1_warp.nii.gz transf/T1_to_DTI.mat | transf DTI/aal2diff
#applywarp --in=$< --ref=$(word 2,$^) --warp=$(word 3,$^) --postmat=$(word 4,$^) --out=$# --interp=nn $(LOGOPT)
#fslmaths $# -thrP 50 -bin $# $(LOGOPT)
$(addsuffix /DTI/aal2diff, $(SUBJS)):
mkdir -p $#
$(addsuffix /transf/T1_to_DTI.mat, $(SUBJS)): %/transf/T1_to_DTI.mat : %/transf/DTI_to_T1.mat | %/transf
convert_xfm -inverse $< -omat $# $(LOGOPT)
$(addsuffix /transf/DTI_to_T1.mat, $(SUBJS)): %/transf/DTI_to_T1.mat : %/DTI/nodif_brain.nii.gz %/T1/T1_brain.nii.gz | %/transf
flirt -in $< -ref $(word 2,$^) -omat $# -searchrx -90 90 -searchry -90 90 -searchrz -90 90 -dof 6 -cost corratio $(LOGOPT)
$(addsuffix /transf/MNI_to_T1_warp.nii.gz, $(SUBJS)): %/transf/MNI_to_T1_warp.nii.gz : %/transf/T1_to_MNI_warp.nii.gz %/T1/T1.nii.gz | %/transf
invwarp --warp=$< --ref=$(word 2,$^) --out=$# $(LOGOPT)
$(addsuffix /transf/T1_to_MNI_warp.nii.gz, $(SUBJS)): %/transf/T1_to_MNI_warp.nii.gz : %/T1/T1.nii.gz %/transf/T1_to_MNI.mat | %/transf
fnirt --in=$< --aff=$(word 2,$^) --cout=$# --config=T1_2_MNI152_2mm $(LOGOPT)
$(addsuffix /transf/T1_to_MNI.mat, $(SUBJS)): %/transf/T1_to_MNI.mat : %/T1/T1_brain.nii.gz | %/transf
flirt -in $< -ref /usr/local/fsl/data/standard/MNI152_T1_2mm_brain -omat $# -searchrx -90 90 -searchry -90 90 -searchrz -90 90 -dof 12 -cost corratio $(LOGOPT)
$(addsuffix /transf, $(SUBJS)):
mkdir -p $#
$(addsuffix /T1/T1_brain.nii.gz, $(SUBJS)): %/T1/T1_brain.nii.gz : %/T1/T1.nii.gz
bet $< $# -B -f 0.3 -g 0 -m $(LOGOPT)
$(addsuffix /DTI/nodif_brain.nii.gz, $(SUBJS)): %/DTI/nodif_brain.nii.gz : %/DTI/data.nii.gz
bet $< $# -f 0.3 -g 0 -m $(LOGOPT)
$(addsuffix /DTI/data.nii.gz, $(SUBJS)): %/DTI/data.nii.gz : %/DTI/diffusion.nii.gz
eddy_correct $< $# 0 $(LOGOPT)
Intuitively, what I would like to have is the possibility of having multiple stems in the targets section, say, %1 and %2 in order to write something like
%1/DTI/aal2diff/AAL_%2.nii.gz: AAL/AAL_to_MNI_%2.nii.gz %1/DTI/nodif_brain.nii.gz %1/transf/MNI_to_T1_warp.nii.gz %1/transf/T1_to_DTI.mat | %1/transf %1/DTI/aal2diff
applywarp --in=$< --ref=$(word 2,$^) --warp=$(word 3,$^) --postmat=$(word 4,$^) --out=$# --interp=nn $(LOGOPT)
fslmaths $# -thrP 50 -bin $# $(LOGOPT)
AFAIK, multiple stems aren't possible.
Do you have any suggestion of how can I go on?
Is it too bad to use make with something other than building programs?
Related
I have been working with a project that only compiles C sources but I've found I need some assembler too, I'm reticent to inline the asm code in a C file as GCC may not interpret it correctly.
My predecesor created the makefile for the project (apologies, it's fairly long):
# Compiler and options
CC := sparc-rtems-gcc
# The application software binary
TARGET := icu_asw
# Source and build directories
SRCDIR := src
BUILDDIR := obj
TARGETDIR := bin
HDSWROOT := ../../hdsw
BSWTOOLS := ../../bsw/sw/tools
SRCEXT := c
DEPEXT := d
OBJEXT := o
MRAMEXT := img.elf
# Flags, libraries and includes
CFLAGS := -std=gnu99 -Wall -Wextra -g
LIBDRV := $(HDSWROOT)/lib/libdrv.a
INCFLAGS := -I$(HDSWROOT)/include -I$(HDSWROOT)/osal/rtems
# Debug flags
DEBUGFLAGS = -DLOGERROR=1 -DLOGWARN=1 -DLOGDEBUG=1 -DLOGINFO=1 -DMAKECHECKS=1
NODEBUGFLAGS = -DLOGERROR=1 -DLOGWARN=0 -DLOGDEBUG=0 -DLOGINFO=0 -DMAKECHECKS=1
#-----------------------------------------------------------------------
# Build instructions
#-----------------------------------------------------------------------
SOURCES := $(shell find $(SRCDIR) -type f -name *.$(SRCEXT))
OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(SOURCES:.$(SRCEXT)=.$(OBJEXT)))
# Default make
all: $(TARGET)
# Remake
remake: cleaner all
# Clean only objects
clean:
#$(RM) -rf $(BUILDDIR)
# Full clean (objects and binaries)
cleaner: clean
#$(RM) -rf $(TARGETDIR)
# Pull in dependency info for *existing* .o files
-include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT))
# Link (uses an order-only prerequisite for the directories so that they
# don't affect the use of the $^)
$(TARGET): $(OBJECTS) | directories
$(CC) -o $(TARGETDIR)/$(TARGET) $^ $(LIBDRV)
# Make the build and target directories
directories:
#mkdir -p $(TARGETDIR)
#mkdir -p $(BUILDDIR)
# Compile
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SRCEXT)
#mkdir -p $(dir $#)
$(CC) $(CFLAGS) $(INCFLAGS) $(NODEBUGFLAGS) -c -o $# $<
#$(CC) $(CFLAGS) $(INCDEP) -MM $(SRCDIR)/$*.$(SRCEXT) > $(BUILDDIR)/$*.$(DEPEXT)
#cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
#sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
#sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
#rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
# Non-File Targets
.PHONY: all remake clean cleaner
I want to also bring in and compile two .S files, so, I edited the following line
SOURCES := $(shell find $(SRCDIR) -type f -name *.$(SRCEXT) -or -name *.$(ASMEXT))
To bring in the .S files, then I edited the OBJECTS to also include the ASM sources ("*.S")
OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(SOURCES:.$(SRCEXT)=.$(OBJEXT)),$(SOURCES:.$(ASMEXT)=.$(OBJEXT)))
But when recompiling with 'make all' I'm getting:
$ make all
make: *** No rule to make target `obj/asi_access.S', needed by `icu_asw'. Stop.
I don't suppose someone could spot where I am going wrong? I think I have not correctly added to the OBJECTS line!
Thanks
The expression $(var:.ext1=.ext2) does not filter by .ext1, i.e.
$(SOURCES:.$(SRCEXT)=.$(OBJEXT)) $(SOURCES:.$(ASMEXT)=.$(OBJEXT))
gives for a test source list the following result
a.o b.o c.S a.c b.c c.o
I.e. you duplicated your files and you have source files in the OBJECTS definition.
The following would be a correct approach:
OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%, \
$(patsubst %.$(SRCEXT),%.$(OBJEXT), \
$(patsubst %.$(ASMEXT),%.$(OBJEXT),$(SOURCES)) \
) \
)
UPDATE: you should consider to use 2 separate object lists, so that you can apply different rules for them, e.g.
SOURCES_C := $(filter %.$(SRCEXT),$(SOURCES))
OBJECTS_C := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(SOURCES_C:%.$(SRCEXT)=%.$(OBJEXT)))
SOURCES_ASM := $(filter %.$(ASMEXT),$(SOURCES))
OBJECTS_ASM := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(SOURCES_ASM:%.$(ASMEXT)=%.$(OBJEXT)))
$(OBJECTS_C): $(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SRCEXT)
.... C compiler recipe ....
$(OBJECTS_ASM): $(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(ASMEXT)
.... assembler recipe ....
$(TARGET): $(OBJECTS_C) $(OBJECTS_ASM) | directories
My makefile currently looks like this:
#Source file locations
VPATH = :../AHMCodePara
#Compiler
CC = mpifort
#Debugging Flags
#Flags =
#Regular flags
Flags = -Ofast -mkl=sequential
# File name labels
FF =
DE =
Const =
OBJDIR = OBJ
# make object directory
$(OBJDIR):
-mkdir $(OBJDIR)
CC += -module $(OBJDIR)
#Object File List
Inputs =
Tools = $(OBJDIR)/$(Const)Inputs.o
Diag$(DE) = $(Tools)
PreAnalysis = $(Tools) $(OBJDIR)/Tools.o
DOSsetupPara$(DE) = $(PreAnalysis) $(OBJDIR)/PreAnalysis.o $(OBJDIR)/Diag$(DE).o
$(Const)AHMRGv3 = $(Tools) $(OBJDIR)/Diag$(DE).o $(OBJDIR)/DOSsetupPARA$(DE).o
#Object File List
obj = $(OBJDIR)/$(Const)Inputs.o $(OBJDIR)/Diag$(DE).o $(OBJDIR)/Tools.o \
$(OBJDIR)/PreAnalysis.o $(OBJDIR)/DOSsetupPARA$(DE).o $(OBJDIR)/$(Const)AHMRGv3.o
# dependence files
$(OBJDIR)/%.o: %.f90 $(%)
# #$(%)
#-rm -f #<~
$(CC) -c $< -o $# $(Flags)
All: V3.e
# Target
V3.e: $(obj)
$(CC) $(Flags) -o $# $^
clean:
rm $(OBJDIR)/*.o $(OBJDIR)/*.mod
It used to be similar to this one:
LOC = ../../AHMCode/
CC = gfortran
#Debugging
#Flags = -O0 -g -fcheck=all -Wall -llapack
#Normal
Flags = -O3 -I/usr/lib/ -L/usr/lib/ -lblas -llapack
FF = _Old
IG = #IGNORE or nothing
TT = #TYPE or nothing
V3$(FF).e: Inputs.o Tools.o PreAnalysis.o DOSsetup$(IG).o Diag$(TT).o AHMRGv3_Manyruns.o
$(CC) $(Flags) AHMRGv3_Manyruns.o Diag$(TT).o DOSsetup$(IG).o PreAnalysis.o Tools.o Inputs.o -o V3$(FF).e
Inputs.o: Inputs.f90
$(CC) $(Flags) -c Inputs.f90
Tools.o: $(LOC)Tools.f90 Inputs.o
$(CC) $(Flags) -c $(LOC)Tools.f90
PreAnalysis.o: $(LOC)PreAnalysis.f90 Inputs.o Tools.o
$(CC) $(Flags) -c $(LOC)PreAnalysis.f90
DOSsetup$(IG).o: $(LOC)DOSsetup$(IG).f90 Inputs.o Tools.o PreAnalysis.o Diag$(TT).o
$(CC) $(Flags) -c $(LOC)DOSsetup$(IG).f90
Diag$(TT).o: $(LOC)Diag$(TT).f90 Inputs.o
$(CC) $(Flags) -c $(LOC)Diag$(TT).f90
AHMRGv3_Manyruns.o: AHMRGv3_ManyRuns.f90 DOSsetup$(IG).o Diag$(TT).o Inputs.o
$(CC) $(Flags) -c AHMRGv3_Manyruns.f90
clean:
rm *.o *.mod
The section I want to compare in these makefiles is the .o file definitions. In the second makefile, I wrote these all out by hand and it worked great. My intention with the second makefile was to do the same thing but more efficiently.
The problems arose with dependencies. When I initially made changes to my makefile, I didn't put any dependencies at all. This led to problems where I would update Inputs and the relevant files wouldn't recompile (e.g. Tools.o). This is as expected so I've been looking for ways to add dependencies in a creative and efficient way that forces the relevant files to recompile.
As you can see I tried creating variables with the same name as the .f90 and .o to use $(%). This seemed kinda janky (and I didn't really think it would work) but unfortunately didn't solve my problem.
As you can see from the original makefile, the dependencies don't follow any sort of pattern. As well you can see that I am compiling Fortran and I'm pretty sure that -gen-dep doesn't do anything and if it does I'm doing it wrong.
Existing questions on the subject have been very unhelpful since the majority uses C++ and that can be very different here.
EDIT: I "fixed" my problem. Its not the most efficient and doesn't automatically generate dependencies but I like it in that its not a lot of repetitive lines.
#Object File List
oInpt =
oTool = $(OBJDIR)/$(Const)Inputs.o
oPreA = $(oTool) $(OBJDIR)/Tools.o
oDOSs = $(oPreA) $(OBJDIR)/PreAnalysis.o $(OBJDIR)/Diag$(DE).o
oDiag = $(oTool)
oMain = $(oTool) $(OBJDIR)/Diag$(DE).o $(OBJDIR)/DOSsetupPARA$(DE).o
obj = $(OBJDIR)/$(Const)Inputs.o $(OBJDIR)/Tools.o $(OBJDIR)/PreAnalysis.o $(OBJDIR)/Diag$(DE).o \
$(OBJDIR)/DOSsetupPARA$(DE).o $(OBJDIR)/$(Const)AHMRGv3.o
# dependence files
$(OBJDIR)/$(Const)Inputs.o: $(oInpt)
$(OBJDIR)/Tools.o: $(oTool)
$(OBJDIR)/PreAnalysis.o: $(oPreA)
$(OBJDIR)/Diag$(DE).o: $(oDiag)
$(OBJDIR)/DOSsetupPARA$(DE).o: $(oDOSs)
$(OBJDIR)/$(Const)AHMRGv3.o: $(oMain)
$(OBJDIR)/%.o: %.f90
#-rm -f #<~
$(CC) -c $< -o $# $(Flags)
All: V3.e
# Target
V3.e: $(obj)
$(CC) $(Flags) -o $# $^
I just made multiple rules for each target. One a default rule that actually compiles the .o files and the other that specifies the dependencies for each .f90 file.
yesterday I wrote a Makefile to build a Programm which works fine.
Now, I try to build different build configurations.
What is the recommended way to build different configurations which differ in the list of source files and output paths?
I tried to use target specific variables...
Executables of the compiler toolchain.
COMPILER := ccrl
LINKER := rlink
ASSEMBLER := asrl
DEVICE_FILE := DR5F100LL.DVF
Compiler flags used to generate *.d files.
DFLAGS := \
-MM \
-MP \
-cpu=S2 \
-dev="$(DEVICE_FILE)" \
-no_warning_num=11179,11180 \
-g \
-Onothing
Compiler flags used to generate *.obj files from c source files.
CFLAGS := \
-cpu=S2 \
-c \
-dev="$(DEVICE_FILE)" \
-no_warning_num=11179,11180 \
-g \
-Onothing
Compiler flags used to generate *.obj files from assembler files.
ASMFLAGS := $(CFLAGS)
Linker flags
LDFLAGS := \
-library="${COMPILER_PATH}/lib/rl78cm4s.lib" \
-library="${COMPILER_PATH}/lib/rl78cm4r.lib" \
-library="./FFT_Library/libfft_rl78g13.lib" \
-nooptimize \
-entry=_start \
-security_id=00000000000000000000 \
-ocdbg=04 \
-user_opt_byte=EEFFE9 \
-debug \
-nocompress \
-memory=high \
-vectn=2=ffff \
-rom=.data=.dataR \
-rom=.sdata=.sdataR \
-nomessage \
-device="$(DEVICE_FILE)" \
-nologo \
-start=.const,.text,.RLIB,.SLIB,.textf,.constf,.data,.sdata/03000,.dataR,.bss/0F7F00,.sdataR,.sbss/0FFE20
Include directories
C_INCS := \
-I${COMPILER_PATH}/inc \
...
C source files used build the program.
C_SRCS_FFT_TEST := \
CodeGenerator/r_cg_cgc.c \
...
C_SRCS_HISTORY_TEST := \
CodeGenerator/r_cg_cgc.c \
...
C_SRCS_IOLINK_TEST := \
CodeGenerator/r_cg_cgc.c \
...
Assembler files used to build the program.
ASM_SRCS := \
...
Root directories of the build results.
OUT_ROOT_DIR := build
PUBLISH_ROOT_DIR := publish
.SECONDEXPANSION:
Name of the build configuration.
BUILD_CONFIG = Unknown
OUT_DIR =$(OUT_ROOT_DIR)/$(BUILD_CONFIG)
PUB_DIR =$(PUBLISH_ROOT_DIR)/$(BUILD_CONFIG)
Determine file paths of generated files.
OBJS = $(patsubst %.c,$(OUT_DIR)/%.obj,$(C_SRCS))
OBJS += $(patsubst %.asm,$(OUT_DIR)/%.obj,$(ASM_SRCS))
DEPS = $(OBJS:.obj=.d)
Filenames of the output files.
OUT_FILE = $(PUB_DIR)/MyFile.abs
MAP_FILE = $(OUT_DIR)/MyFile.map
.PHONY: build-definitions
build-definitions: fft-test history-test iolink-test
fft-test: BUILD_CONFIG=FFT_Test
fft-test: C_SRCS=$(C_SRCS_FFT_TEST)
.PHONY: fft-test
fft-test: $$(OUT_FILE)
history-test: BUILD_CONFIG=History_Test
history-test: C_SRCS=$(C_SRCS_HISTORY_TEST)
.PHONY: history-test
history-test:
#echo -e "Building $(BUILD_CONFIG)."
iolink-test: BUILD_CONFIG=IOLink_Test
iolink-test: C_SRCS=$(C_SRCS_IOLINK_TEST)
.PHONY: iolink-test
iolink-test:
#echo -e "Building $(BUILD_CONFIG)."
.PHONY: all
all: pre-build $(OUT_FILE) post-build
.PHONY: pre-build
pre-build:
#echo -e "Run pre-build target."
.PHONE: post-build
post-build:
#echo -e "Run post-build target."
.PHONY: clean
clean:
#echo -e "Run clean target."
#rm -f -v $(OUT_DIR)/LinkerSubCommand.tmp
#rm -f -v $(OBJS)
#rm -f -v $(DEPS)
#rm -f -v $(OUT_FILE)
#rm -f -v $(MAP_FILE)
How to build the dependency file from a c source file.
$(OUT_DIR)/%.d : %.c
#echo 'Building d file: $<'
#mkdir -p "$(dir $#)"
$(COMPILER) $(DFLAGS) $(C_INCS) -o "$(#:%.obj=%.d)" -MT="$#" -MT="$(#:%.obj=%.d)" "$<"
How to build the dependency file from an asm file.
$(OUT_DIR)/%.d : %.asm
#echo 'Building d file: $<'
#mkdir -p "$(dir $#)"
$(COMPILER) $(DFLAGS) $(C_INCS) -o "$(#:%.obj=%.d)" -MT="$#" -MT="$(#:%.obj=%.d)" "$<"
How to build the object file from a c source file.
$(OUT_DIR)/%.obj : %.c
#echo 'Building obj file: $<'
#mkdir -p "$(dir $#)"
$(COMPILER) $(CFLAGS) $(C_INCS) -o "$#" "$<"
#echo -e $(#:%=-input=\"%\") >> $(OUT_DIR)/LinkerSubCommand.tmp
How to build the object file from an asm file.
$(OUT_DIR)/%.obj : %.asm
#echo 'Building asm file: $<'
#mkdir -p "$(dir $#)"
$(COMPILER) $(CFLAGS) $(C_INCS) -o "$#" "$<"
#echo -e $(#:%=-input=\"%\") >> $$(OUT_DIR)/LinkerSubCommand.tmp
#
$(OBJ): %.obj: %.c $(DEPS)
How to build the output file from all object files.
%.abs : $(OBJS)
#echo -e "Building $(BUILD_CONFIG)."
#echo -e "The output directory is $(OUT_DIR)."
#echo -e "The publish directory is $(PUB_DIR)."
#echo -e "The source files are $(C_SRCS)."
#echo -e "The assembler files are $(ASM_SRCS)."
#echo -e "The generated object files are $(OBJS)."
#echo -e "Building output file is $#."
#mkdir -p "$(PUB_DIR)"
#mkdir -p "$(OUT_DIR)"
$(LINKER) $(LDFLAGS) -subcommand="$(OUT_DIR)/LinkerSubCommand.tmp" -list="$(MAP_FILE)" -output="$(OUT_FILE)"
I know that I should use private as scope of the target specific variables but than I have to download/compile a newer make Version...
I would like to know the recommended way to build such configurations.
Maybe someone can provide a simple (and complete) example?
Thanks a lot!
Michael
Makefile:
ifeq ($(config), debug)
CFLAGS := -DDEBUG -g
OUT_PATH := ./build/debug/
else ifeq ($(config), light_debug)
CFLAGS := -g
OUT_PATH := ./build/light_debug/
else #release config by default
OUT_PATH := ./build/release
endif
#...
Then make invokation is like this:
make confg=debug
or
make config=light_debug
or
make config=release
When I run make -j tests, it makes the tests just fine but removes the dependencies afterwards. Why is it doing this and how can I solve it? I apologize for the complicated makefile. The relevant portions of the makefile are the Test sections.
Makefile:
# Build tools
CC = clang++ -g --std=gnu++11 -O3
LEX = flex
YACC = bison -d
# Includes
CC_HEADERS = `llvm-config-3.5 --cppflags`
CC_LIBRARIES = -lboost_program_options `llvm-config-3.5 --libs all --ldflags` -ltinfo -lpthread -lffi -ldl -lm -lz
# Created files
GENERATED_SOURCES = parser.cpp tokens.cpp
GENERATED_FILES = $(GENERATED_SOURCES)
EXEC = brainfuck.out
# Test cases
TESTS = $(wildcard ./tests/*.bf)
TESTS_IN = $(TESTS:.bf=.in)
TESTS_BUILD = $(TESTS:.bf=.build)
TESTS_EXPECTED = $(TESTS:.bf=.expected)
TESTS_ACTUAL = $(TESTS:.bf=.actual)
TESTS_DIFF = $(TESTS:.bf=.diff)
GENERATED_FILES += $(TESTS_BUILD) $(TESTS_EXPECTED) $(TESTS_ACTUAL) $(TESTS_DIFF)
# Generic config
SOURCES = $(filter-out $(GENERATED_SOURCES), $(wildcard *.cpp))
SOURCES += $(GENERATED_SOURCES)
OBJECTS = $(SOURCES:.cpp=.o)
# Main targets
target: $(EXEC)
all: target tests
# Generated source targets
tokens.cpp: tokens.l parser.hpp
$(LEX) -o $# $<
parser.hpp: parser.cpp
parser.cpp: parser.y
$(YACC) -o $# $<
# Test targets
tests: $(TESTS_DIFF)
#echo ""
#echo "#####################"
#echo "# Begin test output #"
#echo "#####################"
#$(foreach f,$^, echo "Test:" $(f:.diff=.bf); cat $(f); echo "";)
#echo "#####################"
#echo "# End test output #"
#echo "#####################"
#echo ""
tests/%.build: tests/%.bf $(EXEC)
./brainfuck.out $< -p | llc-3.5 - -o - | gcc -O0 -x assembler - -o $#
tests/%.expected: tests/%.bf tests/%.in
-bf -c65535 $< < $(word 2,$^) > $#
tests/%.actual: tests/%.build tests/%.in
-$< < $(word 2,$^) > $#
tests/%.diff: tests/%.expected tests/%.actual
-diff $< $(word 2,$^) > $#
# Generic targets
clean:
rm -rf $(EXEC) $(OBJECTS) $(GENERATED_FILES) $(GENERATED_SOURCES:.cpp=.hpp)
$(EXEC): $(OBJECTS)
$(CC) -o $# ${OBJECTS} $(CC_LIBRARIES)
%.o: %.cpp parser.hpp
$(CC) $(CC_HEADERS) -c $< -o $#
Make output:
bf -c65535 tests/awib-0.4.bf < tests/awib-0.4.in > tests/awib-0.4.expected
./brainfuck.out tests/awib-0.4.bf -p | llc-3.5 - -o - | gcc -O0 -x assembler - -o tests/awib-0.4.build
bf -c65535 tests/dbfi.bf < tests/dbfi.in > tests/dbfi.expected
./brainfuck.out tests/dbfi.bf -p | llc-3.5 - -o - | gcc -O0 -x assembler - -o tests/dbfi.build
bf -c65535 tests/factor.bf < tests/factor.in > tests/factor.expected
./brainfuck.out tests/factor.bf -p | llc-3.5 - -o - | gcc -O0 -x assembler - -o tests/factor.build
bf -c65535 tests/hanoi.bf < tests/hanoi.in > tests/hanoi.expected
./brainfuck.out tests/hanoi.bf -p | llc-3.5 - -o - | gcc -O0 -x assembler - -o tests/hanoi.build
bf -c65535 tests/long.bf < tests/long.in > tests/long.expected
./brainfuck.out tests/long.bf -p | llc-3.5 - -o - | gcc -O0 -x assembler - -o tests/long.build
bf -c65535 tests/mandelbrot.bf < tests/mandelbrot.in > tests/mandelbrot.expected
./brainfuck.out tests/mandelbrot.bf -p | llc-3.5 - -o - | gcc -O0 -x assembler - -o tests/mandelbrot.build
bf -c65535 tests/prime.bf < tests/prime.in > tests/prime.expected
./brainfuck.out tests/prime.bf -p | llc-3.5 - -o - | gcc -O0 -x assembler - -o tests/prime.build
tests/dbfi.build < tests/dbfi.in > tests/dbfi.actual
tests/long.build < tests/long.in > tests/long.actual
tests/factor.build < tests/factor.in > tests/factor.actual
tests/prime.build < tests/prime.in > tests/prime.actual
tests/mandelbrot.build < tests/mandelbrot.in > tests/mandelbrot.actual
tests/hanoi.build < tests/hanoi.in > tests/hanoi.actual
tests/awib-0.4.build < tests/awib-0.4.in > tests/awib-0.4.actual
diff tests/factor.expected tests/factor.actual > tests/factor.diff
diff tests/awib-0.4.expected tests/awib-0.4.actual > tests/awib-0.4.diff
diff tests/mandelbrot.expected tests/mandelbrot.actual > tests/mandelbrot.diff
diff tests/hanoi.expected tests/hanoi.actual > tests/hanoi.diff
diff tests/long.expected tests/long.actual > tests/long.diff
diff tests/prime.expected tests/prime.actual > tests/prime.diff
diff tests/dbfi.expected tests/dbfi.actual > tests/dbfi.diff
#####################
# Begin test output #
#####################
Test: tests/awib-0.4.bf
Test: tests/dbfi.bf
Test: tests/factor.bf
Test: tests/hanoi.bf
Test: tests/long.bf
Test: tests/mandelbrot.bf
Test: tests/prime.bf
#####################
# End test output #
#####################
rm tests/mandelbrot.actual tests/hanoi.build tests/long.actual tests/mandelbrot.build tests/factor.actual tests/awib-0.4.actual tests/long.build tests/prime.actual tests/hanoi.expected tests/factor.build tests/awib-0.4.build tests/dbfi.expected tests/prime.build tests/mandelbrot.expected tests/dbfi.actual tests/long.expected tests/dbfi.build tests/hanoi.actual tests/factor.expected tests/prime.expected tests/awib-0.4.expected
Notice the last line rm .... Where is this coming from?
The solution is to put .SECONDARY: at the top of the makefile. More info here: http://www.thinkplexx.com/learn/howto/build-chain/make-based/prevent-gnu-make-from-always-removing-files-it-says-things-like-rm-or-removing-intermediate-files
Excerpt:
GNU make does track some files, which are created during the build,
and it will remove such files after the build. The files are called
"intermediate files". They are supposed to be created by make’s "chain
of Implicit Rules". Because they were created to facilitate something
else, make considers them useless after the build and removes them.
...
.SECONDARY with no prerequisites causes all targets to be treated as
secondary (i.e., no target is removed because it is considered
intermediate
I came across a makefile which contained the below code. However i am not able to understand the first line $(OBJS): $(OBJDIR)/%.o : $(SRCDIR)/%.cpp, what are the dependencies exactly?
$(OBJS): $(OBJDIR)/%.o : $(SRCDIR)/%.cpp
#$(PRINTF) "$(MESG_COLOR)Compiling: $(NO_COLOR) $(FILE_COLOR) %25s$(NO_COLOR)" "$(notdir $<)"
#$(CC) $(CPPFLAGS) -c $< -o $# -MD 2> temp.log || touch temp.err
#if test -e temp.err; \
then $(PRINTF) $(ERR_FMT) $(ERR_STRING) && $(CAT) temp.log; \
elif test -s temp.log; \
then $(PRINTF) $(WARN_FMT) $(WARN_STRING) && $(CAT) temp.log; \
else printf "${OK_COLOR}%30s\n${NO_COLOR}" "[OK]"; \
fi;
#$(RM) -f temp.log temp.err
This is a static pattern rule. It can be used to build any of the targets in $(OBJS), and constructs the names of the prerequisite(s) accordingly.
SRCDIR = sources
OBJDIR = objects
OBJS = objects/foo.o objects/bar.o objects/baz.o
$(OBJS): $(OBJDIR)/%.o : $(SRCDIR)/%.cpp
#echo the target is $#, the prereq is $<
If you call this rule with "make objects/foo.o", Make will 1) recognize that this rule applies, since the desired target is a member of the rule's list of targets, 2) match the target name "objects/foo.o" against the target pattern "objects/%.o" to obtain the stem "foo", 3) put that stem into the prereq pattern "sources/%.cpp" to obtain the name of the prereq, "sources/foo.cpp".
This is a static pattern rule. Basically it means "for each word in $(OBJS), define an explicit rule where the target pattern $(OBJDIR)/%.o matches the word and the prerequisite is the expansion of the pattern $(SRCDIR)/%.cpp".
So if OBJS is equal to $(OBJDIR)/foo.o $(OBJDIR)/bar.o $(OBJDIR)/baz.o, then the static pattern rule is equivalent to writing this:
$(OBJDIR)/foo.o : $(SRCDIR)/foo.cpp
#$(PRINTF) ...
...
$(OBJDIR)/bar.o : $(SRCDIR)/bar.cpp
#$(PRINTF) ...
...
$(OBJDIR)/baz.o : $(SRCDIR)/baz.cpp
#$(PRINTF) ...
...