Signal current cannot be synthesized, bad synchronous description - vhdl

Question

I have a error while Synthesize this code in Xillinx. This error is:
Analyzing Entity in library (Architecture ).
ERROR:Xst:827 - "C:/Xilinx92i/Parking/Parking.vhd" line 43: Signal current cannot be synthesized, bad synchronous description.
entity Parking is port(
A, B ,reset: in std_logic;
Capacity : out std_logic_vector(7 downto 0));
end Parking;
architecture Behavioral of Parking is
type state is (NoChange, Aseen, Bseen, ABseen, BAseen, Input, Output, Din, Dout);
signal current, nxt : state ;
signal counter : std_logic_vector (7 downto 0) := "00000000";
begin
p1: process(A, B, reset)
begin
if reset = '1' then
current <= Nochange;
end if;
if(A'event and A='1') then
current <= nxt;
end if;
if(A'event and A='0') then
current <= nxt;
end if;
if(B'event and B='1') then
current <= nxt;
end if;
if(B'event and B='0') then
current <= nxt;
end if;
end process;
p2: process(current, A, B)
begin
case current is
when Aseen =>
if B='1' then
nxt <= ABseen;
else
nxt <= NoChange;
end if;
when others =>
nxt <= Nochange;
end case;
end process;
Capacity <= counter;
end Behavioral;

Answer 1

The error 'bad synchronous description' usually means that you have described a register (clocked element) that does not exist in the hardware.
In the case of your code, you have:
if(A'event and A='1') then
current <= nxt;
end if;
if(A'event and A='0') then
current <= nxt;
end if;
-- etc
inside one process. Synchronous synthesisable processes will typically only have one clock, because there is no element in a real silicon device like an FPGA that can respond to events on two different clocks. A process like the one you are trying to implement would typically look something more like this:
process (clk)
begin
if (rising_edge(clk)) then
if (a = '1') then
current <= nxt;
elsif (a = '0') then
current <= nxt;
end if;
end if;
end process;
Implementing it this way requires that you have:
A clock in your system
Inputs that meet setup/hold times relative to this clock
Side note
If you don't have a meaningful name for a process, you don't have to give it one at all. process (clk) is just as valid as p1 : process(clk).