array of signals in VHDL? - vhdl

Question

i'm trying to define a 4096*16 RAM, i did like this:
entity Test is
port(
...
IR : inout std_logic_vector(15 downto 0);
AR : inout std_logic_vector(11 downto 0));
end test
architecture test1 of test is
type ram is array(4095 downto 0) of std_logic_vector(15 downto 0);
signal ram1 : ram := (others => (others => '0'));
begin
AR <= "000000000000";
ram1(0) <= "0010000000000100";
...
...
process(arguments)
IR <= ram1(conv_integer(AR));
my problem is, when i give ram1 values, and then give ram1 values to an output port, its ones (1s) become Unknown (X) in Isim
i get "00X000000X00" for IR in isim

Answer 1

Here is a synchronous design for your RAM entity:
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.numeric_std.ALL;
entity Test is
port(
clock : in std_logic; -- clock
IR : inout std_logic_vector(15 downto 0); -- data port
AR : in std_logic_vector(11 downto 0); -- address port
write_enable : in std_logic -- '1' -> write, '0' -> read
);
end test;
architecture test1 of Test is
type ram is array(0 to 4095) of std_logic_vector(15 downto 0);
-- the actual ram
signal ram1 : ram := (others => (others => '0'));
-- internal signal for reading data
signal IR_out : std_logic_vector(15 downto 0) := (others => 'Z');
begin
-- only apply our own signal to the data port
-- during read
IR <= IR_out when write_enable = '0' else (others => 'Z');
proc: process(clock) is
begin
if rising_edge(clock) then
if write_enable = '1' then
-- write to RAM
ram1(to_integer(unsigned(AR))) <= IR;
else
-- read from RAM
IR_out <= ram1(to_integer(unsigned(AR)));
end if;
end if; -- rising edge
end process;
end; -- architecture
and here is a testbench for it:
library IEEE;
use IEEE.std_logic_1164.all;
entity Testbench is
end Testbench;
architecture TB of Testbench is
component Test
port(
clock : in std_logic; -- clock
IR : inout std_logic_vector(15 downto 0); -- data port
AR : in std_logic_vector(11 downto 0); -- address port
write_enable : in std_logic -- '1' -> write, '0' -> read
);
end component;
-- define signals
signal clock : std_logic := '0';
-- our internal signals
signal IRtest : std_logic_vector(15 downto 0) := (others => 'Z');
signal ARtest : std_logic_vector(11 downto 0) := (others => '0');
signal write_enable_test : std_logic := '0';
begin
-- Instantiate a RAM to be tested and connect it to our signals
uut: Test PORT MAP (
clock => clock,
AR => ARtest,
IR => IRtest,
write_enable => write_enable_test
);
-- clock generator (10 MHz)
clockgen : process
begin
clock <= '0';
wait for 50ns;
clock <= '1';
wait for 50ns;
end process;
-- generate signals to test the RAM
stimulus : process
begin
-- write data into ram
ARtest <= "000000000000";
IRtest <= "0010000000000100";
write_enable_test <= '1';
wait for 100 ns;
-- read a different address back from RAM
ARtest <= "000000000001";
IRtest <= (others => 'Z');
write_enable_test <= '0';
wait for 100 ns;
-- read the original address back from ram
ARtest <= "000000000000";
IRtest <= (others => 'Z');
write_enable_test <= '0';
wait for 100 ns;
wait;
end process;
end; -- architecture
The testbench essentially writes the value to the RAM in the first clock cycle, reads a different address in the second clock cycle and then reads the contents of the original address in the third clock cycle.
The waveform output for the testbench is:
Note that you'll get the contents of the ram at the output port of the RAM entity only on the next rising edge of the clock cycle.
You can fiddle with the design and testbench here: http://www.edaplayground.com/x/5w8
I saw also an asynchronous (not using if rising_edge(clock)) example here: http://www.edaplayground.com/x/3Zs

Answer 2

When using ISim, I assume you use Xilinx FPGA. In that case, take a looks at the Xilinx, HDL Coding Practices for inferring different kind of elements, e.g. RAMs.
Also, only use inout at the toplevel of the design, and even if the RAM is at the top level, then separate the inout from the RAM, so the synthesis tool can implement the different parts of the design, like IO elements and RAMs, correctly.
An example of coding style for inferred RAM, based on the above paper, is:
process (clk)
begin
if (rising_edge(clk)) then
if (we = '1') then
mem(conv_integer(addr)) <= di ;
else
do <= mem(conv_integer(addr));
end if;
end if;
end process;