I have been using Kdevelop with a project, now im on a different laptop, and need to build the project with CLion and MinGW on Windows.
I had this makefile (works on KDevelop)
CC=gcc
DEPS = cmp_micris_defs.h
OBJ = cmp_micris_datos_msc.o cmp_micris_rutinas.o cmp_micris_UnixSocket.o cmp_micris_cfg.o cmp_micris_db.o cmp_micris_TCP.o cmp_micris_utiles.o cmp_micris_datos.o cmp_micris.o
LIBS = -lpthread -lmysqlclient
.PREFIXES = .c .o
.c.o:
$(CC) -std=gnu99 -c -I/home/borja/projects/micris2/proceso-micris2/proceso/ $< $(LIBS)
cmp_micris_borja: $(OBJ)
$(CC) -o $# $(OBJ) $(LIBS)
all: cmp_micris_borja
clean:
rm -rf $(OBJ) cmp_micris_borja
But CLion use Cmake to build, i have not used it before, what should i write in CMakeLists.txt to build like before with my makefile ?
Thanks.
Related
I'm trying to link a .h file from a folder into a Makefile using a .mk file. Folder with .h file (include) is in the same folder as Makefile.
When I run from terminal: make memory.o or make memory.o PLATFORM=MSP432 I get the following error
make: *** No rule to make target '-I./include', needed by 'memory.o'. Stop.
My .mk folder looks like this:
# Add your Source files to this variable
SOURCES = \
./main.c \
./memory.c
# Add your include paths to this variable
INCLUDES =-I./include
My Make file looks like this:
include sources.mk
# Platform Overrides
PLATFORM =
# Architectures Specific Flags
LINKER_FILE = msp432p401r.lds
CPU = cortex-m0plus
ARCH = thumb
SPECS = nosys.specs
# Compiler Flags and Defines
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld
TARGET= c1m2
LDFLAGS = -Wl, -Map=$(TARGET).map -T $(LINKER_FILE)
CFLAGS = -Wall -Werror -g -O0 -std=c99 -mcpu=$(CPU) -m$(ARCH) --specs=$(SPECS)
CPPFLAGs =
ifeq ($(PLATFORM),MSP)
CPU=cortex-m4
CC=arm-none-eabi-gcc
endif
ifeq ($(PLATFORM),HOST)
CC=gcc
endif
OBJS = $(SOURCES:.c=.o)
%.o : %.c $(INCLUDES)
$(CC) -c $< $(CFLAGS) -o $#
.PHONY: build
build: all
.PHONY: all
all: $(TARGET).out
$(TARGET).out: $(OBJS) $(INCLUDES)
$(CC) $(OBJS) $(CFLAGS) $(LDFLAGS) -o $#
.PHONY: clean
clean:
rm -f $(OBJS) $(TARGET).out $(TARGET).map
Can anybody help?
You shouldn't put $(INCLUDES) as a prerequisite of your .o file. This is not right:
%.o : %.c $(INCLUDES)
$(CC) -c $< $(CFLAGS) -o $#
INCLUDES contains options that need to be passed to the compiler (-I...). Prerequisites of targets need to be files that are used during the build. I suppose you want this:
%.o : %.c
$(CC) -c $< $(CFLAGS) $(INCLUDES) -o $#
I have the following Makefile:
VERSION = 0.1.1
CC = g++
CFLAGS = -Wall -g -DVERSION=\"$(VERSION)\"
LDFLAGS = -lm
DEPFILE = .dep
SOURCES := ${wildcard *.cpp}
HEADERS := ${wildcard *.h}
OBJECTS := ${SOURCES:.cpp=.o}
BINARY = main.exe
.PHONY: all dep clean
all: $(BINARY)
$(BINARY): $(DEPFILE) $(OBJECTS)
$(CC) $(CFLAGS) -o $(BINARY) $(OBJECTS) $(LDFLAGS)
%.o: %.cpp
$(CC) $(CFLAGS) -c $<
dep: $(DEPFILE)
$(DEPFILE): $(SOURCES) $(HEADERS)
$(CC) -MM $(SOURCES) > $(DEPFILE)
-include $(DEPFILE)
clean:
rm -vf $(BINARY) $(OBJECTS) $(DEPFILE)
When I run make dep I get
g++ -MM Monomial.cpp main.cpp Variable.cpp > .dep
make: Nothing to be done for 'dep'.
It seems as if dep is called twice. Why is that?
I am using GNU Make 4.2.1 under Cygwin.
Also it would be great if you could give me some best practises for this Makefile if you spot some bad design patterns (other than the double call of dep).
Your makefile contains an include directive:
-include $(DEPFILE)
So when Make starts, before it even considers the target(s) you've asked it to build, it tries to rebuild the file that is to be included in the makefile. Once it's done rebuilding .dep, it gets to work on the file you asked for... which is .dep.
You probably don't have to explicitly make dep, ever.
And you can simplify a couple of your rules in light of this fact, and the useful nature of automatic variables:
$(BINARY): $(OBJECTS)
$(CC) $(CFLAGS) -o $# $^ $(LDFLAGS)
$(DEPFILE): $(SOURCES) $(HEADERS)
$(CC) -MM $(SOURCES) > $#
I've just run into the following issue: I've got a Raspi 3B with a GNU toolchain I normally use to build my C++ project on the Raspi itself. As my project has grown quite large, I would now prefer to cross-build it on my Linux PC with crosstool-ng installed. What I need, though, is a makefile, which both works with the toolchain on the Raspi, and the crosstool. This has been my makefile so far:
CC=g++
CFLAGS=-std=c++11 -ggdb -Wall -Wmultichar
LDFLAGS=-L/usr/lib -L/usr/lib/arm-linux-gnueabihf
LIBRARIES=-lpthread -lkeystonecomm -lgps -lpigpio -lGeographic -lmk4 -lcsvparser -lasound -lespeak -lmpg123 -lout123
SRC=main.cpp vfd.cpp relay.cpp keypad.cpp receiver.cpp widgets.cpp tmc.cpp database.cpp sound.cpp
OBJECTS=main.o vfd.o relay.o keypad.o receiver.o widgets.o tmc.o database.o sound.o
EXEC=autoradio
$(EXEC) : $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS) -o $(EXEC) $(LDFLAGS) $(LIBRARIES)
$(OBJECTS) : $(SRC)
$(CC) $(CFLAGS) -c $(SRC)
.PHONY: clean
clean:
rm -rf *.o $(EXEC)
The issue is the following: The crosscompiler is called arm-unknown-linux-gnueabi-g++, and the library paths are different. My goal, however, is to start the build process with a simple make command both on my Raspi, and on my host machine. Or will I have to use a configure script?
As I haven't found any useful tutorials on the Web, may anybody please help me. Thx.
OK, after consulting a few sources, I decided to implant a conditional into my makefile, which asks for the CPU environment variable. As Raspbian does not set it, I set the Raspi's architecture as a default. Et voilà, it works:
CPU?=armv7l
ifeq ($(CPU), armv7l)
CC=g++
else
CC=arm-unknown-linux-gnueabi-g++
endif
CFLAGS=-std=c++11 -ggdb -Wall -Wmultichar
ifeq ($(CPU), armv7l)
LDFLAGS=-L/usr/lib -L/usr/lib/arm-linux-gnueabihf
else
LDFLAGS=-L/usr/lib -L/opt/x-tools/arm-unknown-linux-gnueabi/lib
endif
LIBRARIES=-lpthread -lkeystonecomm -lgps -lpigpio -lGeographic -lmk4 -lcsvparser -lasound -lespeak -lmpg123 -lout123
SRC=main.cpp vfd.cpp relay.cpp keypad.cpp receiver.cpp widgets.cpp tmc.cpp database.cpp sound.cpp
OBJECTS=main.o vfd.o relay.o keypad.o receiver.o widgets.o tmc.o database.o sound.o
EXEC=autoradio
$(EXEC) : $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS) -o $(EXEC) $(LDFLAGS) $(LIBRARIES)
$(OBJECTS) : $(SRC)
$(CC) $(CFLAGS) -c $(SRC)
.PHONY: clean
clean:
rm -rf *.o $(EXEC)
Following makefile, I am using to generate Fortran executable file in Linux now I need to generate same for windows. How can I write and run the same makefile in windows or if possible can I convert this makefile for windows makefile?
#Makefile for Linux
PROG = sbdart
OBJS = atms.o disort.o disutil.o drt.o params.o spectra.o \
tauaero.o taucloud.o taugas.o
FC = f95
FFLAGS = -o -c
LDFLAGS =
LIBS =
$(PROG): $(OBJS)
$(FC) $(LDFLAGS) -o $# $(OBJS) $(LIBS)
atms.o: params.o atms.f
disort.o: params.o disort.f
disutil.o: params.o disutil.f
drt.o: params.o tauaero.o taugas.o spectra.o drt.f
params.o: params.f
spectra.o: params.o spectra.f
tauaero.o: params.o tauaero.f
taucloud.o: params.o taucloud.f
taugas.o: params.o taugas.f
clean:
rm -f $(PROG) $(OBJS) *.mod
The easiest solution for porting build settings across systems I know of is to create a CMakeLists.txt and generate Makefiles for both automatically using CMake.
You can find an example of Fortran projects with CMake here.
Whenever I am trying to build something like this in my Makefile -
gcc -o main.o -IStarterWare_Files -c main.c StarterWare_Files/test.h StarterWare_Files/add.h
It throws me error that gcc: cannot specify -o with -c or -S with multiple files. Basically I want my makefile to build the target again if I change for example some macro in one of my header files. My current Makefile is -
EXE = nextgenrsm
CC = gcc
LIBS = StarterWare_Files/
CPPFLAGS = _IStarterWare_Files/
MAIN_OBS = $(patsubst %.c,%.o,$(wildcard *.c))
LIB_OBS = $(patsubst %.c,%.o,$(wildcard StarterWare_Files/*.c))
all: $(EXE)
$(EXE): $(MAIN_OBS) $(LIB_OBS)
$(CC) -o $# $(LDFLAGS) $(MAIN_OBS) $(LIB_OBS) $(LDLIBS)
%.o: %.c
$(CC) -o $# -MD -MP $(CPPFLAGS) $(CFLAGS) -c $^
ALL_DEPS = $(patsubst %.o,%.d,$(MAIN_OBS), $(LIB_OBS))
-include $(ALL_DEPS)
clean:
rm -f $(LIB_OBS) $(EXE) $(MAIN_OBS) $(ALL_DEPS)
.PHONY: all clean
I can't figure out what changes to make to build my executable again if one of the header files is modified. I don't want to do make clean and make again.
The way the automake system handles this is to not use %.o: %.c but instead list the C file and all of the headers in the C file.
So for example:
main.o: main.c StarterWare_Files/test.h StarterWare_Files/add.h
$(CC) -o $# -MD -MP $(CPPFLAGS) $(CFLAGS) -c $^
See makedepends for a tool that will read C files and figure out the make dependencies.