I have a short Make script, which works if I put the Build directory in as a string manually myself instead of as a variable:
CC = gcc
CFLAGS = -O2 -g -Wall -fmessage-length=0
LDFLAGS =
SRCDIR = Src
BUILDDIR = Build
SRCS = $(SRCDIR)/Main.c
OBJS = $(SRCS:.c=.o)
LIBS =
TARGET = HelloWorld
all: dir $(SRC) Build/$(TARGET)
dir:
mkdir -p $(BUILDDIR)
Build/$(TARGET): $(OBJS)
$(CC) $(LDFLAGS) $(OBJS) -o $#
$(SRCDIR).c.o:
$(CC) $(CFLAGS) $< -o $#
clean:
rm -f $(OBJS) $(TARGET)
It stops working with the error message:
make: *** No rule to make target `/HelloWorld', needed by `all'. Stop.
when I replace the line:
all: dir $(SRC) Build/$(TARGET)
with:
all: dir $(SRC) $(BUILDDIR)/$(TARGET)
Why is Make not substituting the $(BUILDDIR) clause with Build?
In your code there is a space after Build
BUILDDIR = Build
Related
I was trying to make a more complex Makefile with a src dir and a obj dir.
But doing that the Makefile is now relinking, and I don't understand why.
NAME = program
SRC = main.cpp
SRC_DIR = src/
OBJ = $(SRC:.cpp=.o)
OBJ_DIR = obj/
CC = c++
CFLAGS = -Wall -Werror -Wextra -std=c++98 -fsanitize=address
all: $(NAME)
$(OBJ): $(OBJ_DIR)
$(CC) $(CFLAGS) -c $(SRC_DIR)$(SRC) -o $(OBJ_DIR)$(OBJ)
$(OBJ_DIR):
mkdir $(OBJ_DIR)
$(NAME): $(OBJ)
$(CC) $(CFLAGS) $(OBJ_DIR)$(OBJ) -o $(NAME)
clean:
rm -rf $(OBJ_DIR)
fclean: clean
rm -f $(NAME)
re: fclean all
.PHONY: all clean fclean re
OBJ = $(SRC:.cpp=.o)
This becomes main.o
$(OBJ): $(OBJ_DIR)
$(CC) $(CFLAGS) -c $(SRC_DIR)$(SRC) -o $(OBJ_DIR)$(OBJ)
and this becomes:
main.o: obj/
c++ [options] -o obj/main.o
This will result in the compiler creating obj/main.o. main.o still does not exist. So, on the next make run, make will valiantly try to build it, with the same results (not to mention that an explicit dependency on a directory will create its own set of problems, too).
I'm trying to link a .h file from a folder into a Makefile using a .mk file. Folder with .h file (include) is in the same folder as Makefile.
When I run from terminal: make memory.o or make memory.o PLATFORM=MSP432 I get the following error
make: *** No rule to make target '-I./include', needed by 'memory.o'. Stop.
My .mk folder looks like this:
# Add your Source files to this variable
SOURCES = \
./main.c \
./memory.c
# Add your include paths to this variable
INCLUDES =-I./include
My Make file looks like this:
include sources.mk
# Platform Overrides
PLATFORM =
# Architectures Specific Flags
LINKER_FILE = msp432p401r.lds
CPU = cortex-m0plus
ARCH = thumb
SPECS = nosys.specs
# Compiler Flags and Defines
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld
TARGET= c1m2
LDFLAGS = -Wl, -Map=$(TARGET).map -T $(LINKER_FILE)
CFLAGS = -Wall -Werror -g -O0 -std=c99 -mcpu=$(CPU) -m$(ARCH) --specs=$(SPECS)
CPPFLAGs =
ifeq ($(PLATFORM),MSP)
CPU=cortex-m4
CC=arm-none-eabi-gcc
endif
ifeq ($(PLATFORM),HOST)
CC=gcc
endif
OBJS = $(SOURCES:.c=.o)
%.o : %.c $(INCLUDES)
$(CC) -c $< $(CFLAGS) -o $#
.PHONY: build
build: all
.PHONY: all
all: $(TARGET).out
$(TARGET).out: $(OBJS) $(INCLUDES)
$(CC) $(OBJS) $(CFLAGS) $(LDFLAGS) -o $#
.PHONY: clean
clean:
rm -f $(OBJS) $(TARGET).out $(TARGET).map
Can anybody help?
You shouldn't put $(INCLUDES) as a prerequisite of your .o file. This is not right:
%.o : %.c $(INCLUDES)
$(CC) -c $< $(CFLAGS) -o $#
INCLUDES contains options that need to be passed to the compiler (-I...). Prerequisites of targets need to be files that are used during the build. I suppose you want this:
%.o : %.c
$(CC) -c $< $(CFLAGS) $(INCLUDES) -o $#
I am trying to write a Makefile since it's a good skill to have and all the times I've worked with them it all just seems like black magic to me.
The Makefile is shall mix C source and unit test in C++. I've looked at some examples and tried reading some guides but I am not getting it to work properly and most examples seems quite simple and doesn't really do what I would like to do.
This is the folder structure:
project
src
inc
unit_test
out
Here is my Makefile so far.
CXX = g++
CXXFLAGS = -g -c -I$(INC_DIR)
CC = gcc
CFLAGS = -g -c -Wall -Wextra -Wpedantic -I$(INC_DIR)
LIBS = -lcppunit
OUT_DIR = out
INC_DIR = inc
CPP_SRCS = $(wildcard unit_test/*.cpp)
CPP_OBJS = $(CPP_SRCS:unit_test/%.cpp=$(OUT_DIR)/%.o)
C_SRCS = $(wildcard src/*.c)
C_OBJS = $(C_SRCS:src/%.c=$(OUTDIR)/%.o)
BIN = $(OUT_DIR)/a.out
.PHONY: all run build clean
test:
#echo C_SRCS $(C_SRCS)
#echo C_OBJS $(C_OBJS)
#echo CPP_SRCS $(CPP_SRCS)
#echo CPP_OBJS $(CPP_OBJS)
all: run
run: build
./$(BIN)
build: $(BIN)
clean:
rm -f $(CPP_OBJS)
rm -f $(C_OBJS)
rm -f $(BIN)
$(BIN): $(C_OBJS) $(CPP_OBJS)
$(CXX) $(C_OBJS) $(CPP_OBJS) -o $# $(LIBS)
#echo "Build successful!"
$(CPP_OBJS): $(OUT_DIR)/%.o: unit_test/%.cpp
mkdir -p $(OUT_DIR)
#echo Compiling $<
$(CXX) $< $(CXXFLAGS) -o $#
$(C_OBJS): $(OUT_DIR)/%.o: src/%.c
#echo Compiling $<
$(CC) $< $(CFLAGS) -o $#
Here is the output of 'make test' which will describe my problem at this point in time.
C_SRCS src/add.c
C_OBJS /add.o
CPP_SRCS unit_test/Main.cpp unit_test/Tester.cpp
CPP_OBJS out/Main.o out/Tester.o
Why am I not getting the object file out/add.o when I am doing exactly the same for the the src folder as for the unit_test folder? What am I missing? It's not that obvious to me.
My project is compiled with make and have recently added the boost library for unit testing.
The directory structure is as follows:
Project/
main.cpp
main.hpp
Makefile
sources/
classA.cpp
includes/
classA.hpp
objects/
test/
Makefile
unit_test_classA.cpp
In the folder Project directory I run:
$ make test
Everything works fine except that I don't know how to tell to make to run test/Makefile and look for dependencies in ../object dir automatically.
I'm trying to keep the makefile generic because I build many objects and want to separate my development and testing.
the question is: I need a makefile rule for looking automatically .o files into a especific dir
The Makefiles
# Project/Makefile
BUILD = snake
LDFLAGS =
LDLIBS = -lsfml-graphics -lsfml-window -lsfml-audio -lsfml-system
CXXFLAGS = -Wall -I./includes
RM = rm -rf
OBJ_DIR = objects/
SRC_DIR = sources/
OBJS = $(patsubst $(SRC_DIR)%, \
$(OBJ_DIR)%, \
$(patsubst %.cpp,%.o,$(wildcard $(SRC_DIR)*.cpp)))
OBJECTS = main.o $(OBJS)
all: $(BUILD)
test:
cd test; $(MAKE)
$(BUILD): $(OBJECTS)
$(CXX) $(LDFLAGS) $(LDLIBS) $(OBJECTS) -o $#
$(OBJ_DIR)%.o: $(SRC_DIR)%.cpp $(OBJ_DIR)
$(CXX) $(CXXFLAGS) -c $< -o $#
clean:
$(RM) $(OBJECTS) $(OBJ_DIR)
mkdir $(OBJ_DIR)
.PHONY: test
# Project/test/Makefile
BUILD = boost_test
LDFLAGS =
LDLIBS = -lboost_unit_test_framework
CXXFLAGS = -Wall -I./../includes
RM = rm -rf
OBJS = $(patsubst %.cpp,%.o,$(wildcard *.cpp))
OBJECTS = $(OBJS)
all: clean $(BUILD)
./$(BUILD)
$(BUILD): $(OBJECTS)
$(CXX) $(LDFLAGS) $(LDLIBS) $(OBJECTS) -o $#
%.o: %.cpp
$(CXX) $(CXXFLAGS) -c $< -o $#
clean:
$(RM) $(OBJECTS)
.PHONY: $(BUILD)
I have the below Makefile and for some reason it's dependent on a file, ewapi.c. This file executes some SWIG commands and uses the ewapi.i file. I've clear out all the contents of ewapi.c and the Makefile successfully runs. If I remove the ewapi.c file the make file will not complete. The exception stack is below if that helps. Any ideas on how to change the Makefile so its not dependent on ewapi.c?
# BUILD_DIR and DIST_DIR are exported by build.xml
#
CMODE=
SWIG = swig
CC = $(PREFIX)gcc
LD = $(CC)
OBJ_DIR = $(BUILD_DIR)/obj
AUTOGEN_DIR = $(BUILD_DIR)/auto-generated
PACKAGE_DIR = $(AUTOGEN_DIR)/com/sample/jni
PACKAGE = com.sample.jni
INCLUDES = -I$(JAVA_INCLUDE) \
-I$(SAMPLE_SDK_DIR)/include \
-I$(JDK_HOME)/include
LIB_INCLUDES = -L$(SAMPLE_SDK_DIR)/lib
LIBS = /lib/libssl.so.4 \
/lib/libcrypto.so.4 \
-lSampleApi \
-lm
DIRS = $(PACKAGE_DIR) $(DIST_DIR) $(OBJ_DIR) $(AUTOGEN_DIR)
CFLAGS = $(CMODE) -Wall -fpic $(INCLUDES) -O0 -g3
SFLAGS = -java $(INCLUDES) -package $(PACKAGE) -outdir $(PACKAGE_DIR)
LDFLAGS = -shared $(LIB_INCLUDES) $(LIBS)
OBJECTS = $(OBJ_DIR)/ewapi_wrap.o $(OBJ_DIR)/ewapi.o
TARGET = $(DIST_DIR)/libSample.so
all: $(DIRS) $(TARGET)
%_wrap.c: %.i
$(SWIG) $(SFLAGS) $<
$(OBJ_DIR)/%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
$(TARGET): $(OBJECTS)
$(LD) $(OBJECTS) $(LDFLAGS) -o $#
$(DIRS):
mkdir -p $#
clean:
rm -rf $(TARGET) $(PACKAGE_DIR)/* $(TARGET) $(AUTOGEN_DIR) $(OBJ_DIR)
Exception Stack (when I remove ewapi.c):
[exec] rm ewapi_wrap.c
[exec] make-3.79.1-p7: *** No rule to make target `/test/build/obj/ewapi.o', needed by `/test/dist/libSample.so'. Stop.
The macros OBJECTS includes $(OBJ_DIR)/ewapi.o; the rule for $(TARGET) says it depends on $(OBJECTS); and the rule for all says it depends on $(TARGET). So, there needs to be a way to create ewapi.o from something - and in the absence of ewapi.c, there is no way to build ewapi.o, hence the complaint you get.
Possible fixes:
Replace ewapi.c.
Remove ewapi.o from the macro $(OBJECTS).
Remove $(OBJ_DIR)/ewapi.o from OBJECTS.