Booting ARM Cortex-A secondary cores with Linux - linux-kernel

Question

I need pointers to how Linux implements booting secondary CPU cores in a multi-core SOC.
Is trustzone implementation a must to booting secondary CPU cores?

Answer 1

How Linux implements booting secondary CPU cores in a multi-core SOC?
The specific implementation of multi core boot is platform dependent. Let us take the example of ARM Versatile Express. The VE platform provides a special boot register to help with secondary core bootup. All cores are brought out of reset and execute a code similar to pseudo-code below
if( get_cpu_id() == PRIMARY_CORE )
{
//Primary core enters here
//proceed with booting OS (Linux)
}
else
{
//Secondary core enters here
while( *boot_reg == 0x0 )
{
WFI //Sleep here, wait for interrupts
}
(*boot_reg)(); //Jump to address pointer by boot_reg
}
The Primary core after setting up basic functionality like GIC, will write a secondary core jump address to boot_reg. Then primary core will generate an SGI (Software Generated Interrupt) aimed at the secondary core it wants to bring out of reset. Thus the secondary core is woken up and jumps into the OS's code for secondary core related initialization like page table base address setup, MMU enable etc.
Is trustzone implementation a must to booting secondary CPU cores?
If your ARM core supports Trustzone (Security extensions) all cores will be in Secure Supervisor mode after reset. Ideally you would want to switch to Non-Secure Supervisor mode before you boot up. This mode change has to be executed by all cores. If your ARM core does not support Trustzone, it will be in NonSecure Supervisor mode after reset and thus no special handling will be required. Same goes for Virtualization extensions. If your ARM core supports virtualization and you want to support a hypervisor (this is optional) you will have to Mode Switch to Hypervisor mode (for hyp init) before mode switching to Non Secure Supervisor mode.