I am trying to teach myself gnuMake after learning the basics of C++
I am running Ubuntu 14.04 equivalent (elementary os)
And I am getting the error (full output of make run):
g++ ./main.o -w -o test
This is a test!
/bin/sh: 1: This: not found
make: *** [exe] Error 127
My Makefile:
CC=g++
SRC=$(shell find -name '*.cpp')
OBJS= $(SRC:.cpp=.o)
EXEC=test
FLAGS= -w
LINKS=
%.o: %.cpp
$(CC) -c $*.cpp -o $*.o
$(EXEC): $(OBJS)
$(CC) $(OBJS) $(FLAGS) $(LINKS) -o $(EXEC)
all: $(EXEC)
exe:
$(shell ./$(EXEC))
run: all exe
clean:
rm -rf *.o $(EXEC)
This is a combination of taking basic make tutorials and reading Makefiles in github
main.cpp:
#include <iostream>
using namespace std;
int main()
{
cout << "This is a test!" << endl;
return 0;
}
Pretty Basic, but will be extending it to help learn to use and extend my Makefile. Now I can see the program compiles and runs, but I get the error after the run.
I searched for Make error 127 and that seems to output that error for many things, but I did not see a definition for the error, or a similar issue to mine.
$(shell ./$(EXEC) is incorrect.
That is having make run the executable and then replacing $(shell ./$(EXEC) with the output from the executable and then trying to run that as the command in the recipe.
You just want
exec: $(EXEC)
./$<
Related
I am trying to run some old Fortran code of my project team in ubuntu 16.04. I have not done any modifications to the existing code. All I have done is installed gfortran, opened a terminal, and gone to the file location using the cd command. Here I have many files, but just consider these two: a script file compile.sh, and a makefile remail.make.
In compile.sh:
make -f remail.make
In remail.make:
SOURCE_APPLI= ../SOURCES_COUNTERFLOW/
$(SOURCE_APPLI)grcom.f
TARGET = remail.e
OBJECTS = $(SOURCES_f77:.f=.o)
COMPILE = f90
.f90.o :
$(COMPILE) -o $*.o -c $*.f90
.f.o :
$(COMPILE) -o $*.o -c $*.f
$(TARGET) : $(OBJECTS)
$(COMPILE) $(OBJECTS) -o $#
del :
$(DELETE) $(OBJECTS)
When I run compile.sh, I get this error:
f90 ../SOURCES_COUNTERFLOW/grcom.o -o remail.e
make: f90: Command not found
make: *** [remail.e] Error 127
I have installed fort77 and gfortran-4.8 compilers.
What is the reason for this error?
The problem was that I was not using the correct executable.
For example, In my case, I installed fort77 and gfortran-4.8 and the executable was saved in the name as fort77 and gfortran-4.8.
The reason for my error was that I was calling these two executables as fort77 and gfortran instead of fort77 and gfortran-4.8.
When I called fort77 and gfortran-4.8 correctly in the terminal, it works!!
Suppose that I would like to verify the compatibility of hello.c with multiple compilers. How to do it using a Makefile?
Here is a Makefile I write for this purpose.
# Makefile, version 1.
# It tests hello.c using multiple compilers.
TEST = test_gcc test_clang
.PHONY: $(TEST) all
all: $(TEST)
test_gcc: CC = gcc
test_clang: CC = clang
$(TEST): hello
./hello
rm -f hello
hello: hello.c
$(CC) hello.c -o hello
If I run make test_gcc or test_clang, everything works. However, make all leads to the following.
./hello
Hello, world!
rm -f hello
touch hello.c
./hello
make : ./hello : command not found
make: *** [Makefile:10 : test_clang] Error 127
So hello is not remade for test_clang. This seems to a Makfile beginner like me.
Question: In my Makefile, test_clang depends on hello, which has been removed when test_gcc is finished. So why doesn't make generate it again before running ./hello ?
My Attempts:
To solve the problem, I tried the following modification, which touches hello.c after making test_gcc or test_clang. It still does not work, the problem being the same.
# Makefile, version 2.
# It tests hello.c using multiple compilers.
TEST = test_gcc test_clang
.PHONY: $(TEST) all
all: $(TEST)
test_gcc: CC = gcc
test_clang: CC = clang
$(TEST): hello hello.c
./hello
rm -f hello
touch hello.c
hello: hello.c
$(CC) hello.c -o hello
Following the advice of #HolyBlackCat, I tried also the following.
# Makefile, version 3.
# It tests hello.c using multiple compilers.
TEST = test_gcc test_clang
.PHONY: $(TEST) all
all: $(TEST)
test_gcc: CC = gcc
test_clang: CC = clang
$(TEST): hello_$(CC)
./hello_$(CC)
rm -f hello_$(CC)
hello_$(CC): hello.c
$(CC) hello.c -o hello_$(CC)
The output of make all is
gcc hello.c -o hello_gcc
./hello_gcc
Hello, world!
rm -f hello_gcc
./hello_clang
make : ./hello_clang : commande not found
make: *** [Makefile:13 : test_clang] Error 127
This is even stranger --- hello_clang is never made even though it is required (only) by test_clang.
For your convenience, here is the standard hello.c I used for the test.
/* hello.c */
#include <stdio.h>
int main()
{
printf("Hello, world!\n");
return 0;
}
Thank you very much for any suggestions. It will also be appreciated if you comment on my Makefiles in general, not necessarily regarding the question I raised. I am really a beginner.
See the documentation for target-specific variables: it's quite clear that target-specific variables take effect only in recipes. You cannot use them in prerequisites, or of course when defining targets.
It's probably simpler to do this without target-specific variables and just use pattern rules instead:
TEST = test_gcc test_clang
.PHONY: all
all: $(TEST)
test_%: hello_%
./$<
hello_%: hello.c
$* $< -o $#
(I don't know why you're removing the binary immediately after you test it, in this version, so I removed that).
I'm trying to compile the following code with SDCC, in Debian using only VIM and a Makefile:
void main(void) {
}
Yes, that simple, it's not working yet. I'm using a Makefile like this :
# GNU/Linux specific Make directives.
# Declare tools.
SHELL = /bin/sh
CC = sdcc
LD = gplink
ECHO = #echo
MCU = 16f88
ARCH = pic14
CFLAGS = -m$(ARCH) -p$(MCU)
LDFLAGS = -c -r -w -m I /usr/share/sdcc/lib/$(ARCH)/
EXECUTABLE = t1
SOURCES = test2.c
OBJECTS = $(SOURCES:.c=.o)
CLEANFILES = test2.o test2.asm test2.map test2.lst
.SUFFIXES: .c .o
.PHONY: clean
# Compile
all: $(EXECUTABLE)
.c.o:
$(AT) $(CC) $(CFLAGS) -o $*.o -c $<
$(EXECUTABLE): $(OBJECTS)
$(AT) $(LD) $(LDFLAGS) $(OBJECTS) -o $(EXECUTABLE)
clean:
$(AT) rm -rf $(CLEANFILES)
After all of this the output after running the makefile is:
sdcc -mpic14 -p16f88 -o test2.o -c test2.c
gplink -c -r -w -m I /usr/share/sdcc/lib/pic14/ test2.o -o t1
make: *** [t1] Segmentation fault
I have tried more complex code with the same result,
I can't see what's wrong, anyone ?
I see several things that can be causing you problems:
When you compile for PICs using SDCC, you need the option --use-non-free because some PIC header files have a special Microchip Licence which is not GPL compatible. Furthermore, --use-non-free might not be available on Debian because of their freedom policy if you installed SDCC from repositories. You would need to install the latest SDCC from the official website.
On the linking stage, you should include the PIC libraries needed to run. Try executing sdcc -mpic14 -p16f88 --use-non-free -V test2.c. This way, SDCC links automatically and With -V (verbose) you can see the calls to assembler and linker and can see the libraries that are added on linkage.
I'm reading through Foundations of GTK+ and in so doing decided to write a simple makefile that would let me run "make " to compile the example program I'd just written. I also stumbled upon a list of compiler directives here that the Gnome team specified will help moving from GTK2 to GTK3, so I wanted to include those.
I'm a make noob for all intents and purposes, so this is what I came up with:
CC = gcc
CFLAGS += -Wall
GTK_DFLAGS = -DGTK_DISABLE_SINGLE_INCLUDES -DGDK_DISABLE_DEPRECATED -DGTK_DISABLE_DEPRECATED -DGSEAL_ENABLE
GTK_CFLAGS = $(shell pkg-config --cflags gtk+-3.0)
GTK_LDFLAGS = $(shell pkg-config --libs gtk+-3.0)
%.o: %.c
$(CC) $(CFLAGS) $(GTK_DFLAGS) $(GTK_CFLAGS) -c -o $# $<
%: %.o
$(CC) $(CFLAGS) $(GTK_DFLAGS) $(GTK_CFLAGS) $(GTK_LDFLAGS) -o $# $<
.PHONY: clean
clean:
rm -f *.o *~
And as you might guess, it doesn't work quite right. I know running pkg-config from inside the makefile isn't an ideal solution, but this is for my small-scale learning projects and not for deployment of any sort. That said, the output is weird to me; it seems like make just ignores any variables after CFLAGS.
Something like:
[patrick#blackbox ch2]$ make helloworld
gcc -Wall helloworld.c -o helloworld
helloworld.c:1:21: fatal error: gtk/gtk.h: No such file or directory
#include <gtk/gtk.h>
^
compilation terminated.
<builtin>: recipe for target 'helloworld' failed
make: *** [helloworld] Error 1
If I add have the contents of GTK_DFLAGS simply tacked onto the end of CFLAGS, they appear on the command line, but the pkg-config variables are still missing.
It's obvious to me that I messed something simple up, but after an hour of vaguely worded Googling, I'm fresh out of ideas as to what it is.
Found the answer, and of course the vocabulary I was missing when asking this question/doing earlier searches.
CC = gcc
CFLAGS += -Wall -std=c11
GTK_DFLAGS = -DGTK_DISABLE_SINGLE_INCLUDES -DGDK_DISABLE_DEPRECATED -DGTK_DISABLE_DEPRECATED -DGSEAL_ENABLE
GTK_CFLAGS := $(shell pkg-config --cflags gtk+-3.0)
GTK_LDFLAGS := $(shell pkg-config --libs gtk+-3.0)
%: %.c
$(CC) $(CFLAGS) $(GTK_DFLAGS) $(GTK_CFLAGS) $(GTK_LDFLAGS) -o $* $*.c
.PHONY: clean
clean:
rm -f *~
This does what I want, which is to compile a single .c file of any name into a program of the same name with the GTK flags I was looking to use.
Thanks to those who contributed!
You need a target for helloworld in your Makefile. Something like this:
helloworld: helloworld.o
$(CC) -o helloworld helloworld.o $(LDFLAGS) $(GTK_LDFLAGS)
I've written this hello world in hello.c:
#include <stdio.h>
int main() {
printf("Hello, World!\n");
exit( 0 );
}
my Makefile is:
%: %.c
When I run make I will get this error: make: *** No targets. Stop.
Your makefile provides a rule %: %.c specifying that it's extensionless executables and .c files that you're interested in (in fact, just the built-in rules do that much), but gives no hint that there's a source file named hello.c or a target named hello.
When you type make by itself, make takes the first target listed in the makefile as the target to be made, but your makefile contains no targets whatsoever, hence No targets. Stop. In short, make has no clue that there is anything nearby with a name like hello*.
With your makefile as is, typing make hello will do what you want, as it tells make what it is that you'd like to build.
If you tell make about hello, you'll also be able to type just make to do what you want:
hello: hello.c
%: %.c
or more idiomatically and flexibly, you would list all your "top-level" targets in an all target:
all: hello
%: %.c
.PHONY: all
Typical c hello world prgram:
hello.c:
#include <stdio.h>
int main() {
printf("Hello, World!\n");
return 0;
}
Typical Makefile, short but complete:
Makefile:
all: hello
hello: hello.o
gcc -o "$#" hello.o
hello.o: hello.c
g++ -c hello.c
.PHONY:clean
clean:
rm *.o hello
Example with pattern rules:
all: hello
hello: hello.o
gcc -o "$#" hello.o
%.o: %.c
gcc -c $<
.PHONY:clean
clean:
rm *.o hello
Example with delimiter(\n as enter, \t as tab):
all: hello\n
hello: hello.o\n
\tgcc -o "$#" hello.o
%.o: %.c\n
\tgcc -c $<
.PHONY:clean
clean:\n
\trm *.o hello