There is a Makefile in which I want to include "a.gmake", can I insert a.gmake's content to this Makefile ?
You can just include your gmake file like
include a.gmake
as gmake is a subset of make.
you can find a description of this command here.
Related
I have a makefile where I include a file (with -include titi.mak)
I would like to generate first this file and then include this file in order to benefit the variable in this file.
Thanks in advance
No problem. Put a rule in the makefile to build titi.mak. Then when you execute Make, Make will execute this rule and then reinvoke itself.
-include titi.mak
something:
#echo the value of X is $(X)
titi.mak:
#echo X := 5 > $#
A way of solving this could be found here.
http://make.mad-scientist.net/constructed-include-files/
How would one test for the existence of files with a certain extension (.cpp in this case) in a directory at a specified location which is several directories down from the location of the makefile? I would like to print(echo) a message out if they are found
Your question is ambiguous. You mean, inside a make recipe you want to perform this test? If so then just write the appropriate shell scripting to check for the existence of said files.
If you mean outside of any recipe, in the makefile itself, if you're using GNU make you can use the $(wildcard ...) function:
ifneq (,$(wildcard some/sub/directory/*.cpp))
$(info found some cpp files!)
endif
I would like to tell (g)make to include some common initializations from a separate file knowing the relative location of the included file with respect to the main Makefile.
However in the manuals I cannot find any built-in variable that would, for example, give you the name of the current Makefile.
For example if I want to include the content of a file in the same directory as the current make file, instead of hard-wiring the location of the include:
# MAIN Makefile : ./scripts/make/TaskA.mk
include ./scripts/make/Common.inc
...
I would like to write something like the following assuming that _MAKEFILE_ contains the TaskA.mk location:
# MAIN Makefile : ./scripts/make/TaskA.mk
MAKEFILE_DIR=$(dirname $(_MAKE_FILE_))
include $(MAKEFILE_DIR)/Common.inc
Doesn't the manual give a recipe based on MAKEFILE_LIST?
Basically
this_makefile := $(lastword $(MAKEFILE_LIST))
before any include directives should do the trick.
Look at GNU make - Other Special Variables. MAKEFILE_LIST includes all Makefiles read. So, if you take the first one and extract the directory, you're done.
MAKEFILE_DIR=$(dir $(firstword $(MAKEFILE_LIST)))
include $(MAKEFILE_DIR)Common.inc
Although both names will do the job, what is the correct name for makefiles?
GNU `make' homepage uses Makefile, and I guess it is the good way to name it. Any reasons for typing the front M in upper case ?
What Name to Give Your Makefile chapter of GNU Make manual clarifies it:
By default, when make looks for the makefile, it tries the following names, in order: GNUmakefile, makefile and Makefile. Normally you should call your makefile either makefile or Makefile. (We recommend Makefile because it appears prominently near the beginning of a directory listing, right near other important files such as README.) The first name checked, GNUmakefile, is not recommended for most makefiles. You should use this name if you have a makefile that is specific to GNU make, and will not be understood by other versions of make. Other make programs look for makefile and Makefile, but not GNUmakefile.
I think that Makefile is displayed at the almost top of the list rather than makefile when using the ls command.
it is not only the reason that it appears prominently near the beginning of a directory listing, but also that it would cause a compile error when you using “makefile” to replace “Makefile”。 you could try to test in the helloworld case of Linux device driver..
I have a Makefile in:
project/all_app/myapp/src/Makefile
I also have a master Depend.mk in
project/Depend.mk
Can I include the main Makefile by using the relative path?
include ../../../../Depend.mk
Be warned that make's include starts at pwd, not the path to the Makefile. (so make -f will probably cause problems)
The rules for include in make are a little bit complex - see this section of the GNU make manual. But yes - you can do what you asked.