Does Quartus II suppress report message with the same text? - vhdl

Question

I'm porting a Xilinx ISE project to Quartus II. When I compile that project Quartus crashes with an error: *** Fatal Error: Access Violation at 0X000007FE88160DE1. So I'm trying to narrow down the error to a minimal example, which will guide me to a hidden VHDL bug or to a small example, which I can send to Altera.
The project uses a VHDL data structure (record of vectors of records of vectors of ... of basic types) to describe a SoC setup. The simplified structure look like this:
SoFPGA System
o-DeviceInstances
| o-Device
| o-Registers
| | o-Bitfields
| o-RegisterMappings
o-Busses
I would like to report the full structure to the synthesis log, but Quartus II seems to hide messages if the message text was already printed to the log.
Example:
Info (10635): ... at pb.pkg.vhdl(1228): "DeviceInstance 1:" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1229): " DeviceInstance: Mult32" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1230): " Device: Mult32" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1234): " 0: OperandA0 Reg#=0 WR" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1241): " 0: FieldID=0 (OperandA)" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1234): " 1: OperandA1 Reg#=1 WR" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1234): " 2: OperandA2 Reg#=2 WR" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1234): " 3: OperandA3 Reg#=3 WR" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1234): " 4: OperandB0 Reg#=4 WR" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1241): " 0: FieldID=1 (OperandB)" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1234): " 5: OperandB1 Reg#=5 WR" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1234): " 6: OperandB2 Reg#=6 WR" (NOTE)
Info (10635): ... at pb.pkg.vhdl(1234): " 7: OperandB3 Reg#=7 WR" (NOTE)
The 'FieldID' message is only printed once per 'Operand[A|B]'. There is no FieldID line after operands A1, A2, A3 and B1, B2, B3.
So I tried to add an unique number (salt) to each report line. For that I defined a shared variable and defined a function salty that increments salt in every report statement.
Variable and function:
shared variable salt : NATURAL := 0;
impure function salty return STRING is
begin
salt := salt + 1;
return INTEGER'image(salt);
end function;
Usage:
report salty & "pb_CreateRegisterRO:" severity NOTE;
But unfortunately, salty always returns "0". Quartus II supports VHDL'08 features. Should I implement the shared variable as a protected type and compile it in VHDL'08 mode?
How can I print all report statement lines to the synthesis report?
Off topic question:
Is someone interested in helping me finding the reason why Quartus crashes? I stripped the project to 6 VHDL files. I think this problem is to specific for a SO question. Contact