The following is defined in the makefile:
CXX = g++
CXXFLAGS = -std=c++11
I would like to compile my code with OpenMP directives without changing the original makefile (which runs perfectly). The manual suggests a way to do this, is by changing it on the command line. However, when I run,
make CXXFLAGS=-std=c++11 -fopenmp
the error mentioned before pops up. Can someone help me understand what I'm doing wrong?
The problem here is the space between -std=c++11 and -fopenmp. It splits these two arguments up and the -fopenmp is interpreted as the option -f then openmp is interpreted as a makefile that make attempts to build because it can't find it in the current directory.
You need to execute make with quotes (") like
$ make CXXFLAGS="-std=c++11 -fopenmp"
this will pass CXXFLAGS= -std=c++11 -fopenmp to make. We can see this behaviour with the following simple makefile.
CXX = g++
CXXFLAGS = -std=c++11
all:
#echo $(CXXFLAGS)
Running make will produce the output
$ make
-std=c++11
Running make CXXFLAGS="-std=c++11 -fopenmp" will produce
$ make
-std=c++11 -fopenmp
the correct output and what we were hoping to achieve.
As an aside the command, make CXXFLAGS= -std=c++11 -fopenmp, in your question should produce more errors than just
make: openmp: No such file or directory
make: *** No rule to make target 'openmp'. Stop.
because of the space between CXXFLAGS= and -std=c++11. I get
$ make CXXFLAGS= -std=c++11 -fopenmp
make: invalid option -- =
make: invalid option -- c
make: invalid option -- +
make: invalid option -- +
make: invalid option -- 1
make: invalid option -- 1
If for instance you want to compile with -std=c++14 instead of -std=c++11 you would need to execute make with
$ make CXXFLAGS=-std=c++14
note: no space, or equivalently with
$ make CXXFLAGS="-std=c++14"
again without a space.
Space - The Final Frontier. You need quotes as in
make CXXFLAGS="-std=c++11 -fopenmp"
The shell splits command line words at word boundaries delimited by white space. Quoting is used to avoid word-splitting.
Related
I've got a problem with the way I am shelling out. I'm working with Bash, but its on Debian Sid (Unstable) in a ARM64 Chroot. (I'm doing this because its our Debian package maintainer. Otherwise, I run away from the unstable, bleeding edge stuff)...
# echo $0
/bin/bash
It appears one of my shell commands is creating an -o2 rather than an -O2. I suspect memory is being trashed while shelling out, and the -o2 is just a symptom.
# make cryptlib.o
g++ -DNDEBUG -g3 -o2 -pipe -c cryptlib.cpp
Here's the same command under Remake:
# remake -X -f GNUmakefile cryptlib.o
GNU Make 3.82+dbg0.9
Built for aarch64-unknown-linux-gnu
Copyright (C) 2010 Free Software Foundation, Inc.
...
Updating goal targets....
File `cryptlib.o' does not exist.
Must remake target `cryptlib.o'.
Invoking recipe from GNUmakefile:449 to update target `cryptlib.o'.
##>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
g++ -DNDEBUG -g3 -o2 -pipe -c cryptlib.cpp
##<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
++ (/cryptopp-git/GNUmakefile:448)
cryptlib.o
remake<0>
As can be seen, the stuff I am interested in has already passed. Line 449 is very uninteresting. Its just a standard recipe that uses CXX, CXXFLAGS and $<.
Unfortunately, I don't really see what I should be doing to debug this issue. According to 1.1.6 Debugging Shell Commands, there's a step, but it does not really tell me how to use it. When I attempt to add it to the command:
remake -X step -f GNUmakefile cryptlib.o
It results in No rule to make target 'step'.
How do I debug this makefile with Remake? Or even without it?
The recipe's in your makefile aren't involved with setting that variable's value.
That's is a make variable. It is set at make-parse time by make itself (and the make-level contents of your makefile).
I don't see anything in the linked GNUMakefile that says either -o2 or -g3 both of which are in the make-run compilation command.
That makefile does include a GNUMakefile.deps file if it exists. I suppose that might have the erroneous value in it. Do you have a GNUMakefile.deps file?
Does grep find -g3 or -o2 anywhere in your source directory? (In case there's some other included makefile?)
The last place that make might be getting this value from is the process environment (because CXXFLAGS is defined with the ?= operator).
Do you have CXXFLAGS defined incorrectly in your environment?
This is my first time using make, and i've been spinning my wheels trying to get past an issue. I can't understand why a simple echo never gets executed:
CFLAGS = -Wall
LDFLAGS = -g
CC = gcc
SRCS = p4a.c p4b.c
p4static: p4a.c
gcc $(LDFLAGS) -o $# $< -static -L. -lpthread
p4dynlink: p4a.c
#echo "this doesn't print/echo/execute"
gcc $(LDFLAGS) -o p4dynlink $< -L. -lpthread
I'm using tab instead of spaces. Here is the outputs:
mike#elementary:~/p4$ make
gcc -g -o p4static p4a.c -static -L. -lpthread
mike#elementary:~/p4$ make
make: `p4static' is up to date.
From How make Processes a Makefile:
By default, make starts with the first target (not targets whose names start with ‘.’). This is called the default goal. [....]
Thus, when you give the command:
make
make reads the makefile in the current directory and begins by processing the first rule.
So when you type make make tries to build your p4static target which doesn't have an echo line. And the next time you run make it says that target is up to date and has nothing to do.
To build p4dynlink you need to tell make to build that target make p4dynlink.
You can set the default goal manually (in the makefile) with .DEFAULT_GOAL:
# Set our own.
.DEFAULT_GOAL := foo
But convention is usually to create an all target as the first target and have it "Do the Right Thing" by default.
So in your case, assuming you wanted both targets built by default, you would use:
all: p4static p4dynlink
When I compile code using GNU Make I get multiple warnings like:
clang: warning: -lGui: 'linker' input unused
This is probably because I have messed something up in my Makefile (below). Can anyone point me toward the problem?
CXX=g++
CC=g++
CXXFLAGS=-g -Wall -W -Wshadow -Wcast-qual -Wwrite-strings $(shell root-config --cflags --glibs)
CPPFLAGS+=-MMD -MP
LDFLAGS=-g $(shell root-config --ldflags)
LDLIBS=$(shell root-config --libs)
xSec_x: xSec_x.o xSec.o Analysis.o
-include xSec_x.d xSec.d Analysis.d
xSec.o: xSec.cpp xSec.h Analysis.h Analysis.cpp
xSec_x.o: xSec_x.cpp xSec.h Analysis.h
clean:
rm -f #rm -f $(PROGRAMS) *.o *.d
That message means you are passing linker flags (like -l which tells the linker to pull in a library) to the compiler.
This means that the result of running root-config --cflags --glibs is generating linker flags, and those are going into CXXFLAGS, which is being passed to the compiler. I don't know what root-config is, but you should investigate its command line and invoke it in a way where it doesn't generate linker flags. Probably removing the --glibs option will do it.
ETA: you really want to be using := to assign these flags variables if you're going to run $(shell ...) there. It will work either way, but if you use = then the shell command will be run every time make expands the variable, which is once per compilation. If you use := it will only be run once, when the makefile is parsed.
I got this same error and the reason was that I forgot to add -I in front of my included paths for cflags in makefile. For example:
CFLAGS += $(path)/dir/subdir/include -> Got the above mentioned error.
CFLAGS += -I$(path)/dir/subdir/include -> Fixed the issue.
I'm currently writing a makefile that is able to compile different targets (Like Debug, Development, Release). The linking and compiling rules look like that:
$(DEVELOPMENT_OUT): $(subst rep,development,$(OBJS))
g++ -o $(DEVELOPMENT_OUT) $(subst rep,development,$(OBJS))
obj/development/%.o: src/%.cpp
g++ -c -MMD -MP -MF"$(#:%.o=%.d)" -MT"$(#:%.o=%.d)" -o "$#" "$<"
Now, I get this output:
make: *** No rule to make target 'obj/development/Main.o', needed by 'bin/Development.exe'. Stop.
But shouldn't the pattern rule apply for the Main.o?
I use GNU Make 3.82.90 of MinGW.
There's not enough information here to say why it doesn't work. If you're sure you have a file src/Main.cpp then make should choose that rule. Is the cpp file a source file, or a generated file? If it's generated then maybe the real problem is lower down, where the generating happens. You can try using make -d to see what make is doing and why it doesn't like this rule.
I'm trying to make a makefile for compiling various examples that are within a subfolder. The makefile consisting of just:
S_1_2.exe : Twister.cpp Parsing.cpp ./Surfaces/S_1_2.cpp
g++ -o $#.exe $^ -I . -W -Wall
Works fine when run with the command "make S_1_2.exe". However:
%S_1_2.exe : Twister.cpp Parsing.cpp ./Surfaces/S_1_2.cpp
g++ -o $#.exe $^ -I . -W -Wall
fails, even when run with the command make S_1_2.exe, with the error "make: * No rule to make target 'S_1_2.exe'. Stop."
Shouldn't %S_1_2.exe do pattern matching and so match S_1_2.exe? In which case why is it not matching this rule?
I am using GNU Make 3.81
The percentage symbol matches a non-empty string. So you should use %_1_2.exe or better yet - %.exe. I don't know if there is any other symbol that matches empty strings too.
The % is for matching a part of the target against the same part in one or more dependencies.
You can't omit it from all dependencies.