This is the section of my Makefile which fails
b2dsetup:
#$(ECHO) "Goes in b2dsetup"; \
#if [-d "/external/src/Box2D"]; \
#then $(PRINTF) "Option1"; \
#else; \
#$(ECHO) "Option2"; \
#cd /external/src/; \
#tar cfv Box2D.tgz Box2D; \
#fi;
and gives the following error:
Goes in b2dsetup
bash: line 1: #if: command not found
bash: line 2: #then: command not found
bash: line 3: #else: command not found
bash: line 4: #/bin/echo: No such file or directory
bash: line 5: #cd: command not found
bash: line 6: #tar: command not found
bash: line 7: #fi: command not found
Makefile_g30:71: recipe for target 'b2dsetup' failed
make: *** [b2dsetup] Error 127
shell returned 2
I tried lots of syntactical changes and googling but nothing helps.
Only put the # on the first line of a multiline script.
b2dsetup:
#$(ECHO) "Goes in b2dsetup"; \
if [-d "/external/src/Box2D"]; \
then $(PRINTF) "Option1"; \
else \
$(ECHO) "Option2"; \
cd /external/src/; \
tar cfv Box2D.tgz Box2D; \
fi
Or:
b2dsetup:
#$(ECHO) "Goes in b2dsetup"
#if [-d "/external/src/Box2D"]; \
then $(PRINTF) "Option1"; \
else \
$(ECHO) "Option2"; \
cd /external/src/; \
tar cfv Box2D.tgz Box2D; \
fi
Related
I'm trying to add && \ on end of each line on a text file except the last line.
Sample input:
ps
mkdir repo
cd repo/
touch file1.txt
Expected output:
ps && \
mkdir repo && \
cd repo/ && \
touch file1.txt
First attempt
I tried this, but it outputs && \ on each line including the final line:
awk '{print $0"&& \\"}' RS="\r*\n\r*"
Second attempt
I tried using sed:
sed '1s/^//;$!s/$/"&&" \\/;$s/$//'
This seems to add extra newlines:
ps
&& \
mkdir repo
&& \
cd repo/
&& \
touch file1.txt
You could use sed for something that simple:
printf "line 1\nLine 2\nLine 3\n" | sed '$ ! s/$/ \&\& \\ /'
Output
line 1 && \
Line 2 && \
Line 3
HOMEDIR = $(shell pwd)
DEFAULT = 4.0.3
YESDIR = $(shell echo $(#:install-%=%) | tr A-Z a-z)
NODIR = $(shell echo $(#:clean-%=%) | tr A-Z a-z)
install:
#$(MAKE) install-$(DEFAULT)
install-%:
#cd $(HOMEDIR);\
if [ ! -e $(YESDIR) ]; then \
echo "Library $(#:install-%=%) Version=$(YESDIR) does not exist"; \
elif [ -e $(YESDIR)/Install.sh ]; then \
echo "Installing $(PKGNAM) version=$(YESDIR)" ; \
cd $(YESDIR) ;\
$(SHELL) Install.sh $(HOMEDIR) 1 ;\
elif [ -e $(YESDIR)/Makefile ]; then \
cd $(YESDIR); \
$(MAKE); \
else \
echo "Installation instruction for $(#:install-%=%) Version=$(YESDIR) does not exist"; \
fi;
the above makefile gives me the following error
line 6: syntax error: unexpected end of file
Remove trailing blanks in this line:
$(SHELL) Install.sh $(HOMEDIR) 1 ;\
I am trying to loop through the .c files in a specific directory through the makefile.
i used the following code, but it seems not working:
DIR= Sources \
Sources_2
#for entry in ${DIR} ; \
do \
#for i in $${entry}/*.c ; \
do \
echo "Processing $${i}"; \
#Building Commands go here
done \
done
I get error: "/bin/sh: -c: line 3: syntax error near unexpected token `do'"
You shouldn't use at sign # near the second for loop. # should be used at the beginning of the whole shell command. The following worked for me:
DIR= Sources \
Sources_2
all:
#for entry in ${DIR}; \
do \
for i in $${entry}/*.c; \
do \
echo "Processing $${i}"; \
done \
done
Change the Makefile as below
#for entry in ${DIR} ; do \
for i in $$entry/*.c ; do \
echo "Processing $$i"; \
#Building Commands go here
done \
done
The reason being wrong syntax usage of for loop.
I have the following make file, which i think is a shell script.
I am trying to loop through FILE_DIR to perform some operations. However, i feel that the implementation isn't working as expected. So i am trying to insert some echo breakpoints.
Source:
# Target to recurse through the DIR_LIST and make each makefile found in that DIRS
ALLDIRS:
for se in $(FILE_DIR); do \
if [ -d $se ]; then \
cd $se; \
$(MAKE) -f Makefile.mk all; \
cd ..; \
fi \
done
Running:
$ make -f Makefile.batch
h: syntax error at line 3: `then' unexpected
*** Error code 2
The following command caused the error:
for se in `ls -p /app/internal|grep "/"`; do \
echo "Test" \
if [ -d e ]; then \
cd e; \
/usr/ccs/bin/make -f Makefile.mk all; \
cd ..; \
fi \
done
make: Fatal error: Command failed for target `ALLDIRS'
Can i please get help on this. Would like to insert an echo breakpoint.
One common error in Makefiles is using spaces instead of tabs in a command line. Check the whole for loop and make sure there are only tabs at the beginning of each line
ALLDIRS:
<tab>for se in $(FILE_DIR); do \
<tab><tab>if [ -d $se ]; then \
<tab><tab>cd $se; \
<tab><tab>$(MAKE) -f Makefile.mk all; \
<tab><tab>cd ..; \
<tab><tab>fi \
<tab>done
Another error is the dollar sign $. If you want a dollar sign in the shell command, you must double it in your commands, because otherwise dollar introduces a make variable and will be expanded before the shell sees it.
for se in $(FILE_DIR); do \
if [ -d $$se ]; then \
cd $$se; \
$(MAKE) -f Makefile.mk all; \
cd ..; \
fi \
done
And the final one, echo Test needs a semicolon as well
for se in $(FILE_DIR); do \
if [ -d $$se ]; then \
echo "Test"; \
cd $$se; \
...
I am executing the following command in Makefile:-
#ls export_mojave/marker_*.tcl > export_mojave.list
#for file in `cat export_mojave_tcl_files.list`; do \
diff $$file bk_marker > $$file.diff ; \
if ! [ -s $$file.diff ]; then\
rm -f $$file.diff ; \
else \
echo $$file >> marker.fill.tcl.diff; \
fi \
done ;
If there exists some file related to the above expression in the mentioned directory,
it will run fine but if there does not exits any files matching to above expression, It is marking an error. Is there anything exists like "catch" in Makefile?
If you need to skip error in makefiles' rule, then prefix command with '-' sign:
-#ls .... > some_file || echo Error: no file;
if [ -e some_file ] ....
Or modify to be more in make-style:
FILES := $(shell ls ...)
ifeq ($(FILES),)
$(error no files)
endif
....
target:
$(foreach file,$(FILES), ...)