Parameterised makefile function - makefile

Question

I'm using a makefile to run docker, where I first collect some modules to download, so that they can be cached and then run docker. I wanted to parameterize this, but I don't think I'm doing this in the best way. Pointers to make this more concise would be really appreciated.
franz:
$(eval REPO_VERSION := $(shell grep franz requirements/github.txt | cut -d'#' -f3 | cut -d'#' -f1))
if [ -d docker/franz ]; then \
echo "Updating franz to [$(REPO_VERSION)]"; \
cd docker/franz && git fetch && git checkout $(REPO_VERSION); \
else \
echo "Cloning franz to [$(REPO_VERSION)]"; \
git clone --branch $(REPO_VERSION) git#github.com:dubizzle/franz.git docker/franz 2> /dev/null; \
fi \
lilith:
$(eval REPO_VERSION := $(shell grep lilith requirements/github.txt | cut -d'#' -f3 | cut -d'#' -f1))
if [ -d docker/lilith ]; then \
echo "Updating lilith to [$(REPO_VERSION)]"; \
cd docker/lilith && git fetch && git checkout $(REPO_VERSION); \
else \
echo "Cloning lilith to [$(REPO_VERSION)]"; \
git clone --branch $(REPO_VERSION) git#github.com:dubizzle/lilith.git docker/lilith 2> /dev/null; \
fi \
dependencies: franz lilith
git archive --format tar.gz --output docker/archive.tar.gz $(GIT_REF)
Basically, this first updates requirements that are on github, downloads them, checks what version is needed, and then updates to that version. If this could be made a function, a parameterised version would be:
$(eval REPO_VERSION := $(shell grep <repo-name> requirements/github.txt | cut -d'#' -f3 | cut -d'#' -f1))
if [ -d docker/<repo-name> ]; then \
echo "Updating <repo-name> to [$(REPO_VERSION)]"; \
cd docker/<repo-name> && git fetch && git checkout $(REPO_VERSION); \
else \
echo "Cloning <repo-name> to [$(REPO_VERSION)]"; \
git clone --branch $(REPO_VERSION) git#github.com:dubizzle/<repo-name>.git docker/<repo-name> 2> /dev/null; \
fi \
I've seen some examples using define, and call, and eval, but, I can't figure out the right combination to make it work.
Any help with this would be much appreciated.

Answer 1

From the tutorial mentioned above, to pull the information to SO.
This is GNU make, mind.
Defining a template:
define RULES_template
$(1)/obj/%.o: $(1)/src/%.c
$$(CC) $$(CFLAGS) $$(CFLAGS_global) $$(CFLAGS_$(1)) -c $$< -o $$#
endef
This uses one parameter ($(1)), which gets substituted as appropriate. The number of parameters is not declared, you just add $(1), $(2) etc. to the template. Note the duplication of $$ everywhere else.
$(foreach module,$(MODULES),$(eval $(call RULES_template,$(module))))
This calls the template mentioned above for each token in $(MODULES).
call RULES_template,foo instantiates the template with one parameter, foo. eval then parses the output as Makefile syntax (as opposed to, for example, putting it into some variable).
This has been ages ago, and I never used that code in a productive environment, so I am a bit fuzzy on the details. I hope it helps, anyway.
CMake not only is cross-platform, but also has much better primitives to handle sophisticated build mechanics. I can recommend it.