Unable to split a Vector in VHDL - vhdl

Question

I am unable to update reg_1 and reg_2 vectors by splitting reg_mem?
This is my code in VHDL which i had written in MODELSIM:
In other program i tried to split another vector into two parts and store them into two different Vectors.It worked fine.But same syntax is not working in this code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Register_unit is
port (
reg_read : in std_logic;
reg_write : in std_logic;
reg_mem : inout std_logic_vector(3 downto 0);
reg_start : inout std_logic_vector(3 downto 0);
reg_end : inout std_logic_vector(3 downto 0);
reg_write_comp : out std_logic;
reg_read_comp : out std_logic;
reg_1 : inout std_logic_vector(1 downto 0);
reg_2 : inout std_logic_vector(1 downto 0));
end Register_unit;
architecture Register_unit_arch of Register_unit is
begin
process (reg_read,reg_write)
begin
if (reg_read = '1' and reg_write = '0') then
reg_end <= reg_mem;
reg_read_comp <= '1';
elsif (reg_write = '1' and reg_read = '0') then
reg_mem <= reg_start;
reg_write_comp <= '1';
end if;
reg_1 <= reg_mem(1 downto 0); --reg_1 is not getting updated
reg_2 <= reg_mem(3 downto 2); --reg2 is not getting updated
end process;
end Register_unit_arch;

Answer 1

reg_1 and reg_2 is updated but they are updated to previous value of the reg_mem. This line;
reg_mem <= reg_start;
is not in effect until the end of process. You are making the reg_1 and reg_2 assignment before reg_mem has it's new value!
VHDL doesn't work top down like a programming language even if you are in a process.
In your case you should either use a variable (*) or directly assign from reg_start like this;
reg_1 <= reg_start(1 downto 0);
reg_2 <= reg_start(3 downto 2);
(*) variables are immediately assigned in a process, you can use them similar to programming language variables