Easy way of dividing an integer by 3 - vhdl

Question

I'm working on a project that is to make a simple music player on an FPGA. It takes a music file of a specified format from the PC and plays it out loud in loops.
We need to implement the standard note lengths, i.e. Quaver for half a beat, Minim for 2 beats, etc. Currently we have a table of the lengths of a beat in numbers of clock cycles at various BPM values. We need to multiply them by these note lengths to yield the correct clock cycles. The only problem is Tuplet, which is a third of a full beat.
Without implementing a full-blown divider circuit, are there any maths tricks one can do to divide, approximately, an integer by 3?

Answer 1

Dividing by 3 is the same as multiplying by 1/3 (=0.33333). 0.3333 can be expressed as an addition of two or more (depending on the needed accuracy) (left) shifted input values.
input*2^-a + input*2^-b + input*2^-c ...
Just find suitable values for a, b, c, ...
This works for (almost) all divisions.

Answer 2

The following is a VHDL translation of some code from Hank Warren’s Hacker’s Delight. It divides an unsigned integer by the constant value 3 using only shifts, additions, and multiplications by the constant values 3 and 5 (which can also be reduced to shifts and additions).
-- q is quotient, d is dividend
q := (d srl 2) + (d srl 4); -- q = d*0.0101 (approx)
q := q + (q srl 4); -- q = d*0.01010101
q := q + (q srl 8);
q := q + (q srl 16);
r := resize(d - q * 3, 32); -- 0 <= r <= 15.
q := resize(q + (5 * (r + 1) srl 4), 32);

Answer 3

If the exact result of integer division by 3 (x / 3) is required for an unsigned value of length LEN, then truncating integer operations can be used with a little trick. The constant for 1/3 should be of length LEN + 1 and 1 should be added. Truncation can then be used afterwards. Pseudo code as:
C = 2 ** (LEN + 1) / 3 + 1
y = (x * C) / 2 ** (LEN + 1)
A Python function that shows and tests the algorithm for all values is:
def div_by_3_test(LEN):
DIVISOR = 3
C = 2 ** (LEN + 1) // DIVISOR + 1
for x in range(2 ** LEN):
if (x * C) // 2 ** (LEN + 1) != x // DIVISOR: exit('Failed')
A VHDL module that implements this as:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity div_by_3 is
generic(
LEN : natural := 12);
port(
x_i : in std_logic_vector(LEN - 1 downto 0);
y_o : out std_logic_vector(LEN - 1 downto 0));
end entity;
architecture syn of div_by_3 is
-- Constant to multiply, basically 1/3, but adding 1 to avoid error
constant C : std_logic_vector(LEN - 1 + 1 downto 0) :=
std_logic_vector(to_unsigned(2 ** (LEN + 1) / 3 + 1, LEN + 1));
-- Intermediate, with length as 2 * LEN + 1
signal t : std_logic_vector(2 * LEN + 1 - 1 downto 0);
begin
-- Intermediate with full length result
t <= std_logic_vector(unsigned(C) * unsigned(x_i));
-- Result after truncation for division by LEN + 1
y_o <= t(2 * LEN + 1 - 1 downto LEN + 1);
end architecture;
The advantage is that a division by 3 of an LEN bit number can be made in one cycle using only a single 2 * LEN + 1 bit multiplication.
Registers may be added to allow pipeline for high speed design.
Note that a similar scheme is possible for any divisor, but length of C must then be LEN + ceil(log2(DIVISOR)), with C scaled accordingly. Please see https://math.stackexchange.com/q/2444306/275980 regarding the mathematical foundation.

Answer 4

As mentioned by dieli, multiply by 0.333333.
However, instead of using several negative powers of 2 (i.e. a, b, c,..) just multiply 1/3 by some large power of 2, e.g. 2^24 * (1/3) = 5592405. After multiplying the clock cycles and 5592405, just divide by 2^24.
B = (clock cycles)*5592405
result = B/2^24
The size of B would depend the maximum size of clock cycles and can be computed by
maximum register size for B = integer of ( (log10((max size of clock cycles)*5592405)/log10(2)) + 0.5)