program Adventure;
uses Crt;
var
guess : integer ;
begin
TextColor(White);
TextBackground(Green);
writeln('Adventure');
writeln('You are an adventurer. You are having an adventure in the forrest but you get lost in the way. You need to answer questions to escape from the forrest.');
writeln('The game will start now.');
writeln('Question1: You are hungry now. You find a mushroom. Will you eat it?');
writeln('Press ',1,'=yes, ',2,'=no.');
readln(guess);
if guess = 1 then
begin
{condition 1}
writeln('It is a toxic mushroom. You died.');
writeln('This is the end of the game.');
readln;
end
else if guess = 2 then
begin
{condition 2}
writeln('You do not eat the mushroom but you catch some fishes in the river.');
writeln('You are full now and have energy to find the way to escape frome forest.');
writeln('Question2:You see a bear and it keeps follow you. Will you climb up to a tree?');
writeln('Press ',1,'=yes, ',2,'=no.');
readln(guess);
if guess = 2 then
begin
{condition 1}
writeln('You are killed by the bear.');
writeln('This is the end of the game.');
readln;
end
else if guess = 1 then
begin
{condition 2}
writeln('You escape from the bear.');
writeln('Question3:Will you get in the cave?');
writeln('Press ',1,'=yes, ',2,'=no.');
readln(guess);
readln;
if guess = 1 then
begin
{condition 1}
writeln('You are killed by the lion which live in the cave');
writeln('This is the end of the game.');
readln;
end
else if guess = 2 then
begin
{condition 2}
writeln('Although you get wet, but you find the way to escape from the forrest finally.');
writeln('Congratulations!');
writeln('This is the end of the game.');
readln;
end;
end.
It is a mini-game about a adventure.Also, the program could not show the expected answer. The error pascal is throwing out is:Fatal: Syntax error, ; expected but . found. I thought that maybe my logic is wrong.Thank you;)
You were missing two 'end;' statements. I have re-formatted to show the problem (and solution).
program Adventure;
uses Crt;
var
guess : integer ;
begin
TextColor(White);
TextBackground(Green);
writeln('Adventure');
writeln('You are an adventurer. You are having an adventure in the forrest but you get lost in the way. You need to answer questions to escape from the forrest.');
writeln('The game will start now.');
writeln('Question1: You are hungry now. You find a mushroom. Will you eat it?');
writeln('Press ',1,'=yes, ',2,'=no.');
readln(guess);
if guess = 1 then
begin
{condition 1}
writeln('It is a toxic mushroom. You died.');
writeln('This is the end of the game.');
readln;
end
else if guess = 2 then
begin
{condition 2}
writeln('You do not eat the mushroom but you catch some fishes in the river.');
writeln('You are full now and have energy to find the way to escape frome forest.');
writeln('Question2:You see a bear and it keeps follow you. Will you climb up to a tree?');
writeln('Press ',1,'=yes, ',2,'=no.');
readln(guess);
if guess = 2 then
begin
{condition 1}
writeln('You are killed by the bear.');
writeln('This is the end of the game.');
readln;
end
else if guess = 1 then
begin
{condition 2}
writeln('You escape from the bear.');
writeln('Question3:Will you get in the cave?');
writeln('Press ',1,'=yes, ',2,'=no.');
readln(guess);
readln;
if guess = 1 then
begin
{condition 1}
writeln('You are killed by the lion which live in the cave');
writeln('This is the end of the game.');
readln;
end
else if guess = 2 then
begin
{condition 2}
writeln('Although you get wet, but you find the way to escape from the forrest finally.');
writeln('Congratulations!');
writeln('This is the end of the game.');
readln;
end;
end;
end;
end.
Related
I am trying to work on inserting if else to loop but it is still expecting some syntax. I cant figure out why this if/else statement wont compile. I am new to VHDL, please help. This is one of the steps along the way and i am stuck.
variable i : integer := 0;
begin
while i < 10 loop
report "i=" & integer'image(i);
i := i + 1;
if i = 6 then
report "okay good job";
else i = 5 then
report " okay nice work";
else
report " not equal to 5 and 6";
end loop;
wait;
end process;
end architecture;
In VHDL, the keywords are if, elsif and else
if condition_1 then
-- do something
elsif condition_2 then
-- do something else
else
-- do something when all other conditions are false
end if;
I'm trying to write a code for multiplying two 100x100 matrices in vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.mult_100x100_pack.all;
entity multiplier_main_code is
Port ( in_matrix1 : in t_2d_array;
in_matrix2 : in t_2d_array;
out_matrix : inout t_2d_array);
end multiplier_main_code;
architecture Behavioral of multiplier_main_code is
begin
process(in_matrix1, in_matrix2)
begin
for i in 0 to 99 loop
for j in 0 to 99 loop
for k in 0 to 99 loop
out_matrix(i)(j) <= std_logic_vector(signed(out_matrix(i)(j)) + (signed(in_matrix1(i)(k)) * signed(in_matrix2(k)(j))));
end loop;
end loop;
end loop;
end Behavioral;
Its again and again showing an error saying:
expecting type void for "behavioral"
syntax error near "Behavioral"
The code for mult_100X100_pack package is:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package mult_100x100_pack is
type t_1d_array is array(integer range 0 to 99)of std_logic_vector(7 downto 0);
type t_2d_array is array(integer range 0 to 99)of t_1d_array;
end mult_100x100_pack;
Please, can anybody help me to get around this error?
After fixing your indentation, it should be quite obvious what you are missing:
process(in_matrix1, in_matrix2)
begin
for i in 0 to 99 loop
for j in 0 to 99 loop
for k in 0 to 99 loop
-- Do things
end loop;
end loop;
end loop;
-- Perhaps `end process;` might be appropriate here...
Your process needs an end process; :
end loop;
end process;
end Behavioral;
This illustrates the advantage of taking care to indent code correctly. If all your end fors lined up with their corresponding fors, this would have been obvious.
I am trying to make a fsm in vhdl using modelsim but when i try and compile my code i have this errors
** Error: C:/Users/manor/Desktop/ldh/mult_fsm.vhd(34): near "when": (vcom-1576) expecting END.
** Error: C:/Users/manor/Desktop/ldh/mult_fsm.vhd(60): near "when": (vcom-1576) expecting END.
** Error: C:/Users/manor/Desktop/ldh/mult_fsm.vhd(72): near "else": (vcom-1576) expecting END.
And this is my code
library ieee;
use ieee.std_logic_1164.all;
entity mult_fsm is
port(ck,adx,m: in std_logic;
adsh,sh,cm,mdone: out std_logic);
end entity mult_fsm;
architecture ideal of mult_fsm is
type StateType is (S0, S1, S2, S3, S4);
signal CurrentState, NextState: StateType;
begin
NS_CS: process( ck)
begin
if ck'event and ck='1' then
case CurrentState is
when S0=>
if (adx='0') then
NextState <= S0;
else
NextState <= S1;
end if;
when S1=>
NextState <= S2;
when S2=>
if (m='1') then
NextState<=S3;
else if (m='0') then
NextState<=S2;
end if;
when S3=>
NextState <= S4;
when S4=>
NextState <= S0;
end case;
end if;
end process NS_CS;
OL: process (CurrentState)
begin
case CurrentState is
when S0=>
if (adx = '0') then
adsh<='0';
sh<='0';
cm<='0';
mdone<='0';
else if (adx = '1') then
if (m='1') then
adsh<='1';
else if (m='0') then
sh<='1';
end if;
end if;
when S1=>
if (m='1') then
adsh<='1';
else if (m='0') then
sh<='1';
end if;
when S2=>
if (m='0') then
adsh<='0';
sh<='0';
cm<='0';
mdone<='0';
else if (m='1') then
adsh<='1';
end if;
when S3=>
if (m='0') then
sh='1';
else if (m='1') then
cm<='1';
adsh<='1';
end if;
when S4=>
mdone<='1';
end case;
end process OL;
end architecture ideal;
I tried fixing the code myself but i just can't figure out what is the problem with it.
Replace your else ifs with elsifs.
In VHDL, each if needs an end if. If you write
if ... then
...
else if ... then
you need two end ifs - one for each if:
if ... then
...
else IF ... THEN
...
END IF;
end if;
VHDL has an elsif statement. That does not start a new if statement, but instead is part of the if statement it follows. If you replace else IF in the above example, you only need one end if:
if ... then
...
elsif ... then
...
end if;
Looking at the following code:
if (m='1') then
NextState<=S3;
else if (m='0') then
NextState<=S2;
end if;
I think you meant elsif instead of else if. Alternatively, since m is an std_logic, you may be able to simplify this block down to:
if (m='1') then
NextState<=S3;
else
NextState<=S2;
end if;
I have expression. How I can open or rewrite this?
if not ((A or B) and PAR like '%3%') then
--do some code
end if;
Can do this more simple?
Please, give me a link for another expressions as example.
The following should be close to what you're looking for:
IF A = FALSE AND B = FALSE AND REGEXP_LIKE(PAR, '[^3]') THEN
-- code here
END IF;
Share and enjoy.
try the following code
if(A!=true or B!=true)
if(REGEXP_LIKE(name,'[^r]'))
/*code has to be written here*/
end if;
end if;
I have this code in VHDL. What I want is to rise rst when sw'event and afterwards, the rst is to fall by itself. But when I simulate this, rst never falls!
process(rst,clk,sw)
begin
if (clk'EVENT and clk='1') then
if (rst='1') then
rst<='0';
elsif (sw'event) then
rst<='1';
elsif (my_counter="11") then
deb_sw<=sw;
end if;
end if;
end process;
sw'event is very unlikely to be true at exactly the same time as clk'event is.
This is because signals are usually driven by another process which is also doing a clk'event, so the signal will be updated after the clk event.
If you want to detect when sw changes from '0' to '1' (or vice versa), you have to keep track of its previous value:
if sw /= last_sw then
-- do what you need to do when it changes
end if;
last_sw := sw;
finally i solved it like this
process(rst,clk,sw)
begin
if (clk'EVENT and clk='1') then
if (rst='1' and rst'last_value='0') then
rst<='0';
elsif (sw='1') then
rst<='1';
deb_sw<=sw;
elsif (my_counter="1010") then -- clock cycles=10*f
deb_sw<=sw;
end if;
end if;
end process;