Unexplainable behavior in GNU make - macos

Question

I have the following Makefile:
SHELLS = $(call adjust, profile bash zsh)
adjust = $(foreach arg, $(1), $(DIR)/$(DOT)$(arg))
sys:
$(eval DIR = /etc)
$(eval DOT = )
usr:
$(eval DIR = $(wildcard ~))
$(eval DOT = .)
# Installation Recipes {{{1
shell-sys: $(SHELLS) | sys
#echo $(SHELLS)
shell-usr: $(SHELLS) | usr
#echo $(SHELLS)
$(SHELLS): $(DIR)/$(DOT)%: $(wildcard %/*)
#echo $(SHELLS)
Now I run make shell-sys and expect the following result:
$ make shell-sys
/etc/profile /etc/bash /etc/zsh
/etc/profile /etc/bash /etc/zsh
/etc/profile /etc/bash /etc/zsh
/etc/profile /etc/bash /etc/zsh
However what I get is the following:
$ make shell-sys
/profile /bash /zsh
/profile /bash /zsh
/profile /bash /zsh
/etc/profile /etc/bash /etc/zsh
Inside Static Pattern Rules $(DIR) and $(DOT) fail to expand, however in ordinary rules they seem to expand just fine. What am I doing wrong? Is there a better way to achieve what the sys and usr targets do?

Answer 1

Before running any recipes (shell commands),
make will read the entire Makefile.
While it does this it expands the dependency lines.
Recipes themselves are simply stored away as recursively expanded variables.
At the end of this stage make has a dependency graph.
In your case, make expands
shell-sys: $(SHELLS) | sys
$(SHELLS) becomes /profile /bash /zsh given the emptiness of $DIR and $DOT.
You can get some hint about make expanding these empty variables by giving make the --warn command-line parameter.
Thus it is as if you had written:
shell-sys: /profile /bash /zsh | sys
#echo $(SHELLS)
/profile /bash /zsh: /%:
#echo $(SHELLS)
(I doubt you have a folder on your disk called % so I'm assuming the $(wildcard ...) expands to nothing.)
Once it has a dependency graph in its little hands,
make can walk it,
executing the recipes as it goes.
You asked it to build shell-sys,
so it first tries to build /profile.
[Probably. Makefiles that rely on this implicit ordering of dependencies are broken IMHO.]
Make now builds /profile.
It knows how to do this, you told it earlier.
It expands the recipe.
#echo $(SHELLS) becomes #echo /profile /bash /zsh.
Make passes echo /profile /bash /zsh to the shell without telling you it has done this due to the # prefix.
echo dutifully prints /profile /bash /zsh.
Similarly for the targets /bash and /zsh.
Next we get to build sys.
Make expands the recipe for sys.
Each separate line in the expansion is passed to a new invocation of the shell.
The expansion however is empty,
so the shell is not called.
As a side effect DIR becomes /etc.
Finally the recipe for shell-sys.
Hopefully you can now see that that expands to #echo /etc/profile /etc/bash /etc/zsh
There's a lot not to like in your formulation,
but the biggest advice I can give is not to cause a $(eval ...) to expand at recipe execution time.