VHDL - test bench - generics - vhdl

Question

I've been working on making a decoder that I can use in multiple instances by just changing a generic value for the size of the input/output vector. The decoder will 'sll' a single bit, a number of positions based on the integer conversion of the input. The decoder itself works fine. The problem arrises when I make a test bench and compile. Resulting in:
Error (10482): VHDL error at DECODER.vhd(41): object "n" is used but not declared
I've added the model and test bench below:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY DECODER IS
--GENERIC (delay : delay_length := 0 ns);
GENERIC (n : POSITIVE := 2);
PORT (a : IN std_logic_vector(n-1 DOWNTO 0);
x : OUT std_logic_vector(2**n-1 DOWNTO 0));
END ENTITY DECODER;
ARCHITECTURE dflow OF DECODER IS
CONSTANT x_out : BIT_VECTOR (2**n-1 DOWNTO 0) :=
( 0 => '1', OTHERS => '0');
BEGIN
x <= to_stdlogicvector(x_out sll to_integer(unsigned(a)));
END ARCHITECTURE dflow;
--test bench----------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TN2 IS
END ENTITY TN2;
ARCHITECTURE IO_TN2 OF TN2 IS
COMPONENT DECODER IS
--GENERIC (delay : delay_length := 0 ns);
GENERIC (n : POSITIVE := 2);
PORT (a : IN std_logic_vector(n-1 DOWNTO 0);
x : OUT std_logic_vector(2**n-1 DOWNTO 0));
END COMPONENT DECODER;
SIGNAL a : std_logic_vector (n-1 DOWNTO 0); --<-- USED BUT NOT DECLARED
SIGNAL x : std_logic_vector (2**n-1 DOWNTO 0);
BEGIN
G1 : DECODER
GENERIC MAP (n => 2)
PORT MAP (a,x);
a <= "00", "01" AFTER 1 NS, "10" AFTER 2 NS, "11" AFTER 3 NS,
"00" AFTER 4 NS, "0Z" AFTER 5 NS;
END ARCHITECTURE IO_TN2;
CONFIGURATION CFG_DECODER OF TN2 IS
FOR IO_TN2
FOR G1 : DECODER
USE ENTITY work.DECODER(dflow)
GENERIC MAP (n => 2)
PORT MAP (a,x);
END FOR;
END FOR;
END CONFIGURATION CFG_DECODER;
The compiler is telling me that I have not declared n, which I thought I did in the component declaration. Where should I declare it?
A second question is how can I declare multiple generics i.e
1 generic for delay_length
1 generic for n
I tried putting 2 generic statements inside the model entity but the compiler did not think that was the right thing to do.
As always many thanks for the help.
D

Answer 1

Your component declaration is stating that there is a component called decoder, which (along with other properties of this component) has a generic called n, with a default value of 2. At this point in analysis of the file, you have said nothing about the actual value you want to assign to n.
My approach would be to define a constant, prior to declaring the component:
constant DECODER_WIDTH : integer := 2;
You then use this to declare your signal:
SIGNAL a : std_logic_vector (DECODER_WIDTH-1 downto 0);
when you instantiate your decoder, you then also bind the n generic to this constant:
G1 : DECODER
GENERIC MAP (n => DECODER_WIDTH)
PORT MAP (a,x);
If you really need to have the configuration change the value of n, you will have to declare the DECODER_WIDTH constant inside a package, which this file would then use, both before the TN2 entity declaration, and before the configuration statement. If you don't need the configuration to alter the decoder size, then you can just omit the generic map from the configuration statement.

Answer 2

Thanks for the comments I've updated the code below with the amendments you suggested and it works well
--test bench for 2/4 decoder----------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TN2 IS
END ENTITY TN2;
ARCHITECTURE IO_TN2 OF TN2 IS
COMPONENT DECODER IS
--GENERIC (delay : delay_length := 0 ns);
GENERIC (n : POSITIVE := 2);
PORT (a : IN std_logic_vector(n-1 DOWNTO 0);
x : OUT std_logic_vector(2**n-1 DOWNTO 0));
END COMPONENT DECODER;
CONSTANT DECODER_WIDTH : integer := 2; ---<-- ADDED constant changing this value will alter decoder vector size
SIGNAL a : std_logic_vector (DECODER_WIDTH-1 downto 0); --< changed n to decoder_width
SIGNAL x : std_logic_vector (2**DECODER_WIDTH-1 DOWNTO 0); --< changed n to decoder_width
BEGIN
G1 : DECODER
GENERIC MAP (n => DECODER_WIDTH) --< pass decoder_width to n
PORT MAP (a,x);
a <= "00", "01" AFTER 1 NS, "10" AFTER 2 NS, "11" AFTER 3 NS,
"00" AFTER 4 NS, "0Z" AFTER 5 NS;
END ARCHITECTURE IO_TN2;
CONFIGURATION CFG_DECODER OF TN2 IS
FOR IO_TN2
FOR G1 : DECODER
USE ENTITY work.DECODER(dflow)
GENERIC MAP (n => decoder_width)
PORT MAP (a,x);
END FOR;
END FOR;
END CONFIGURATION CFG_DECODER;