I have makefile.am. I want to clean the files without using "make clean" in automake file.
After building, .la, .a, .so files will be generated. I want to remove all the files. If I run make clean, then those will be removed.
But, I need them to be removed at the end of make.
makefile.am:
libdir=${prefix}/lib/cli
lib_LTLIBRARIES= libmain.la
libmain_la_SOURCES = main.c
clean-local:
rm -f *.la
rm -f *.a
Related
I wrote this Makefile:
all: clean basedemo.exe
clean:
rm -f *.exe
%.exe: %.s
vasmm68k_mot -kick1hunks -Fhunkexe -o $# -nosym $<
My goal would be to compile every .s file in the current folder to a separate .exe.
Right now, I have to append the new .exe file name to the line: all: clean basedemo.exe new_file.exe
Is there a way to avoid having to do that?
Thank you
I tried using a wildcard:
all: clean $(wildcard *.exe)
But when I run make all only the clean recipe runs.
$(wildcard *.exe) searchs for existing .exe files, but they do not exist yet when you run make.
What you can do is to find all .s files and substitute their extension to .exe:
FILES_S:=$(wildcard *.s)
FILES_EXE:=$(FILES_S:%.s=%.exe)
all : clean $(FILES_EXE);
I have a Makefile in the workspace folder. There are individual projects where there are project.mk files.
In the main Makefile, I want to use targets from the individual project.mk files.
all: buildUIProject1 buildUIProject2
Where buildUIProject1 is a target in project.mk
buildUIProject1: $(shell find src -name *)
npm run build
How can I accomplish this?
What you'd do is a recipe for the buildUIProject1 that runs make (recursively) on project.mk. In the main makefile:
buildUIProject1:
$(MAKE) -C project1/folder -f project.mk $#
My current Makefile.am looks something like this:
bin_PROGRAMS = MyProgram
AM_CPPFLAGS = -I../shared
MyProgram_SOURCES = main.cpp Source1.cpp ../shared/Source2.cpp
clean : clean-am
rm -f *~
rm -f DEADJOE
distclean: distclean-am
rm -f *~
rm -f DEADJOE
rm -f Makefile
rm -f *log
This creates all the .o files in the current directory. How can I specify a different object directory in a Makefile.am? I failed to find this in the GNU documentation, although I am sure it must be there somewhere.
You can't do this in Makefile.am. This approach is not generally supported by autoconf and automake at all.
Instead, Automake supports configuring and building outside the source tree. So in your current tree, "make distclean", then:
mkdir ../build
cd ../build
../src/configure
make
I have a simple makefile with 3 build rules:
clean (that cleans the .o)
debug (compiles my code with debgging stuff)
release (compiles my code with optimization stuff)
sometimes I want to switch between debug mode and release so I would issue this
make clean debug -j8
or
make clean release -j8
that has a drawback because while it's doing the clean stuff, the -j8 allows make to jump some command since the .o are still there Then those .o are removed by the clean rule and the compiler complains because it can't find those .o
I could do something like
make clean; make debug -j8
but since I use an odd makefile in another dir, the command becomes
make -C ../src -f nMakefile clean ; make -C ../src -f nMakefile -j8 release
that is more annoying. I was wondering if there was an hiddedn-guru-mode-rule that allows me to do it in one line
Hope it's clear enough...
I needed to solve this very same problem, and the solution I came up was to parse the MAKECMDGOALS for clean, and dispatch a shell command to do the actual cleaning work; RATHER than clean the build as a target. This way, any MAKECMDGOALS that include "clean" will clean the build as part of that build, first, sequentially, rather than clean running asynchronously as its own target.
-include $(deps)
bin/%.o : %.cpp
#mkdir -p $#D
g++ $(flags) $(includes) -MMD -c $< -o $#
.PHONY : clean
clean:
#echo rm -rf bin/
ifneq ($(filter clean,$(MAKECMDGOALS)),)
$(shell rm -rf bin/)
endif
As I stated above, the normal practice is to have different sub directories for the object files. As you are running in parallel I would think you need to enforce serial execution so that clean is completed before release. One way of doing it could be:
clean_release: clean
+#$(MAKE) -s --no-print-directory release
or if you prefer
clean_release:
+#$(MAKE) -s --no-print-directory clean && $(MAKE) -s --no-print-directory release
I wonder why this won't delete/clean *.o files generated when running make?
# UNIX Makefile
CXX = g++
LD = g++
CXXFLAGS = -g
testlfunction: lfunction.o lfunctionlist.o lprocessor.o testlfunction.o
$(LD) -o $# $^
clean:
rm *.o testlfunction
before it use to be
$(RM) *.o testlfunction
but it didn't work also ;(
Why is this?
To check what really happens, run "make clean" and examine the output of that command.
Is it nothing? Then there might be a file called "clean" in the current directory. Remove it and try again.
Does it start with "rm ..."? Then it seems to be normal.
In all other cases, tell us the exact output you get.
To check whether the commands are really run, insert some "echo" commands before and after the "rm" command. Are they executed?
And finally, did you distinguish between tab characters and spaces? In Makefiles the difference is important. Commands must be indented using tabs.
One way that make clean can 'fail' to execute anything is if there is a file called clean in your directory, possibly the result of running make -t clean. This would create a file, so when you next ran make clean, it would appear up to date - it has no dependencies, so there is no reason to run the action.
If you use GNU Make, ensure that you have the line:
.PHONY: clean
That will stop make -t from creating clean and will ensure that the actions are run.