error: expected expression when using lambda expression in C++ - macos

When using a lambda expression my compiler shows me an error. This is the implementation (where name is a std::string&):
auto expression = [name](const Item* x) -> bool { return x->get_name() == name; };
This is the error:
items/container.cpp:20:27: error: expected expression
auto expression = [name](const Item* x) -> bool { return x->get_name() == name; };
These are my compiler flags:
CFLAGS=$(-std=c++11 -stdlib=libc++ -g -Wall -Werror -Wextra -I.)
All other C++11 features I have used have worked so far. I am using MacOS 10.11.3.
>> clang --version
Apple LLVM version 7.0.2 (clang-700.1.81)
Target: x86_64-apple-darwin15.3.0
Thread model: posix
>> clang++ --version
Apple LLVM version 7.0.2 (clang-700.1.81)
Target: x86_64-apple-darwin15.3.0
Thread model: posix
Unfortunately this did not help me: Clang 3.1 and C++11 support status
UPDATE: After creating a minimal example as suggested by the comments below it worked! The problem must lie in my makefile. This reproduces the error:
CC=clang++
CFLAGS=$(-stdlib=libc++ -std=c++11 -g -Wall -Werror -Wextra -I.)
all: main
main: main.o
$(CC) $(CFLAGS) -o main *.o
main.o: main.cpp
$(CC) $(CFLAGS) -c main.cpp
My main.cpp file:
#include <iostream>
#include <string>
int main() {
auto lambda = [](const std::string& str) { return str == "whatever"; };
std::string s1 = "something else";
std::string s2 = "whatever";
std::cout << "should be false: " << lambda(s1) << std::endl;
std::cout << "should be true: " << lambda(s2) << std::endl;
return 0;
}

You're misusing the $ sign in your makefile. It's for substitutions of variables so $(-stdlib=libc++ ...) would suggest you had a variable whose name started with -stdlib=... (I'm surprised this isn't giving you an error)
If you don't want a substitution and just want literal content, write it after the = sign unescaped:
CC=clang++
CFLAGS=-stdlib=libc++ -std=c++11 -g -Wall -Werror -Wextra -I.
all: main
main: main.o
$(CC) $(CFLAGS) -o main *.o
main.o: main.cpp
$(CC) $(CFLAGS) -c main.cpp

Related

make error : *** missing separator. Stop

This is my makefile:
OBJECTS = main.o
CFLAGS = -g -wall
NAME = make
CC = gcc
build: $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS) -o $(NAME)
I'm getting below error when I tried to make(Applied tab before gcc command) :
makefile:6: *** missing separator. Stop.
How can I fix this?
First of all, it looks like you have spaces instead of tab.
As for the Makefile itself, I'd make it little bit simpler. For a source file main.c:
int main() {
return 0;
}
I would go with Makefile:
CFLAGS = -g -wall
CC = gcc
main: main.c
$(CC) $(CFLAGS) $< -o $#

gcc warning different when using --preprocessed

When compiling ltrace with icecc we run into a compilation problem. This is the minimal example:
main.c
#include <assert.h>
int main(int argc, char **argv) {
assert(argc != argc);
return 0;
}
test.sh:
#!/bin/bash
set -x
# one step compilation (no warning)
gcc -Wall main.c
# splitted compilation (warning)
gcc -Wall -E main.c -o main.i
gcc -Wall --preprocessed main.i
output:
++ gcc -Wall main.c
++ gcc -Wall -E main.c -o main.i
++ gcc -Wall --preprocessed main.i
main.c: In function ‘main’:
main.c:4:10: warning: self-comparison always evaluates to false [-Wtautological-compare]
assert(argc != argc);
^~
As you can see the result is different when compiling in one step and when preprocessing and compiling in two steps. Is this intended behavior?
I use gcc 6.3, the issue also appears in gcc 6.2 for ARM. I also cannot ignore this, as the full example uses -Werror.

Executing a command one by one

I have the following Makefile:
CC := clang++
CFLAGS := -std=c++1z
BINARY := -g -Wall -Wextra -Wformat -Werror -pedantic
OPTIMIZE := -Ofast -march=native -ffast-math
CPPCOREGUIDELINES := clang-tidy
SRC := $(wildcard *.cpp)
BIN := $(patsubst %.cpp,bin/%,$(SRC))
all: clean cpp
clean:
mkdir -p ./bin
rm -f bin/*
cpp: $(BIN)
$(BIN): bin/%: %.cpp
$(CC) $(CFLAGS) $(BINARY) $(OPTIMIZE) $^ -o $#
checks: $(SRC)
$(CPPCOREGUIDELINES) $^ -- $(CFLAGS) $(BINARY) $(OPTIMIZE)
Which executing checks like this:
$ make checks
clang-tidy 007-pointer.cpp 008-arrays-introduction-smarter.cpp -- -std=c++1z -g -Wall -Wextra -Wformat -Werror -pedantic -Ofast -march=native -ffast-math
81 warnings generated.
393 warnings generated.
C:\www\cpp\hackerrank\007-pointer.cpp:16:3: warning: do not call c-style vararg functions [cppcoreguidelines-pro-type-vararg]
scanf("%d %d", &a, &b);
^
C:\www\cpp\hackerrank\007-pointer.cpp:18:3: warning: do not call c-style vararg functions [cppcoreguidelines-pro-type-vararg]
printf("%d\n%d", a, b);
^
C:\www\cpp\hackerrank\008-arrays-introduction-smarter.cpp:19:12: warning: do not use pointer arithmetic [cppcoreguidelines-pro-bounds-pointer-arithmetic]
cin >> t[i];
^
C:\www\cpp\hackerrank\008-arrays-introduction-smarter.cpp:22:13: warning: do not use pointer arithmetic [cppcoreguidelines-pro-bounds-pointer-arithmetic]
cout << t[i] << " ";
^
...
I want to execute checks one by one after each file like this:
$ make checks
clang-tidy 007-pointer.cpp -- -std=c++1z -g -Wall -Wextra -Wformat -Werror -pedantic -Ofast -march=native -ffast-math
81 warnings generated.
C:\www\cpp\hackerrank\007-pointer.cpp:16:3: warning: do not call c-style vararg functions [cppcoreguidelines-pro-type-vararg]
scanf("%d %d", &a, &b);
^
C:\www\cpp\hackerrank\007-pointer.cpp:18:3: warning: do not call c-style vararg functions [cppcoreguidelines-pro-type-vararg]
printf("%d\n%d", a, b);
^
clang-tidy 008-arrays-introduction-smarter.cpp -- -std=c++1z -g -Wall -Wextra -Wformat -Werror -pedantic -Ofast -march=native -ffast-math
312 warnings generated.
C:\www\cpp\hackerrank\008-arrays-introduction-smarter.cpp:19:12: warning: do not use pointer arithmetic [cppcoreguidelines-pro-bounds-pointer-arithmetic]
cin >> t[i];
^
C:\www\cpp\hackerrank\008-arrays-introduction-smarter.cpp:22:13: warning: do not use pointer arithmetic [cppcoreguidelines-pro-bounds-pointer-arithmetic]
cout << t[i] << " ";
^
...
How can I do that?
Do them one by one then:
checks: $(patsubst %.cpp,%.check,${SRC})
%.check : %.cpp
$(CPPCOREGUIDELINES) $< -- $(CFLAGS) $(BINARY) $(OPTIMIZE)
.PHONY: %.check checks

undefined reference static library makefile

I am trying to link a static library while creating my program executable using the below makefile..
IDIR =../inc
CC=g++ -g
CFLAGS=-I$(IDIR)
WFLAGS=-Wall -W
OFLAGS=-O3
DLINUX=-D_LINUX
ODIR=obj
LDIR =../lib
LIBS=-lm
_OBJ = testclient.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
$(ODIR)/testclient.o: testclient.c
$(CC) -c $< $(CFLAGS) -o $#
$(ODIR)/file2.o: file2.c
$(CC) -c $< $(CFLAGS) -o $#
testclient: $(OBJ)
$(CC) -o $# $^ $(LIBS) -lccn -pthread
.PHONY: clean
clean:
rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~
I have tried everything available from changing the order of the '-lccn' parameter to checking whether the function exists in the library (nm libccn.a gives the required function ccn_create() in it). The error returned is :
obj/testclient.o: In function `main':
/root/testClient/src/testclient.c:91: undefined reference to `ccn_create()'
The library libccn.a is in /usr/local/lib. I have also tried changing the directory path and then using -L flag to look in that location. Doesn't work either. :( ..Any ideas as to how can i make it work ?
My guess is that libccn.a is a C library and the header that you use are not designed to be imported by a C++ compiler (there is no extern "C" { } block surrounding the function definition).
C++ supports function overloading by mangling name of function. When you put a function in a extern "C" { } block, C++ disable name mangling (and thus disable overloading). Here, in your error message, the function mentioned is ccn_create(). Notice the (), this means that the function type is known, and thus the named looked up was a mangled name.
When you do nm libccn.a you see the real name, and it is ccn_create. That is not a mangled name. So to fix this, you'll need to surround the function definition in a export "C" { } block. The easiest way to do that is to surround the #include in such a block.
BTW, you can reproduce the error by doing this.
$ echo 'void ccn_create();' > ccn.h
$ echo '#include "ccn.h"
void ccn_create() { }' > ccn.c
$ echo '#include "ccn.h"
int main () {
ccn_create();
return 0;
}' > main.cc
$ gcc -o ccn.o -c ccn.c
$ g++ -o main main.cc ccn.o
Undefined symbols for architecture x86_64:
"ccn_create()", referenced from:
_main in cc8XnYRq.o
ld: symbol(s) not found for architecture x86_64
$ echo 'extern "C" {
#include "ccn.h"
}
int main () {
ccn_create();
return 0;
}' > main.cc
$ g++ -o main main.cc ccn.o

Does not compile with a preprocessor value on the command-line

Where am I going wrong; I want to define a preprocessor value on the command-line for g++ but it fails. Below is sample code that replicate my problem:
[edit] I'm using:g++ (Debian 4.3.2-1.1) 4.3.2GNU Make 3.81
test.h
#ifndef _test_h_
#define _test_h_
#include "iostream"
#if defined(MY_DEFINED_VALUE)
#if (MY_DEFINED_VALUE != 5)
#undef MY_DEFINED_VALUE
#define MY_DEFINED_VALUE 3
#endif //(MY_DEFINED_VALUE != 5)
#else //defined(MY_DEFINED_VALUE)
#error Error - MY_DEFINED_VALUE is not defined
#endif //defined(MY_DEFINED_VALUE)
class test
{
public:
int val;
test() {}
void show() { std::cout << "val = " << val << "\n"; }
};
#endif //_test_h_
test.cpp
//#define MY_DEFINED_VALUE 5
#include "test.h"
int main()
{
test t;
t.val = MY_DEFINED_VALUE;
t.show();
return 0;
}
Makefile
#=====
CC = g++
LD = g++
USERDEFINES = -DMY_DEFINED_VALUE
CFLAGS = -Wall
LDFLAGS =
RM = /bin/rm -f
SRCS = test.cpp
OBJS = test.o
PROG = test
#=====
$(PROG): $(OBJS)
$(LD) $(LDFLAGS) $(OBJS) -o $(PROG)
#=====
%.o: %.c
$(CC) $(USERDEFINES) $(CFLAGS) -c $<
#=====
clean:
$(RM) $(PROG) $(OBJS)
If I uncomment the #define in test.cpp, all is well (prints 5). If I comment it I get the #error.
The problem is in your Makefile. The %.o: %.c rule doesn't match a .cpp file, so GNU Make's built-in %.o: %.cpp rule is being triggered instead.
If you change %.o: %.c to %.o: %.cpp, it'll run fine.

Resources