i was curious if it is possible you can make a 3 input nor gate just by using usual 2-input nor gates, but it seems like there's always one source that, no matter what the other two are, it has the same result.
is there a way that this is possible?
NOR(A,B,C)≡NOR(A,NOR(B,C))
... so you can create a three-input NOR circuit with two two-input NOR gates where the output of the first is linked to the input of the second.
Related
I'd like to be able to poison a signal in VHDL so that any subsequent consumers of it get a poisoned value too so I can find unintended links. Its fine if poisoning works in simulation only.
Background: I've made a CPU in VHDL and want to pipeline it. Before I do that I want to make sure that no part of the pipeline is sampling outputs from other parts when it shouldn't. So all the parts in the pipeline create and hold their valid output for exactly one clock cycle and set the various outputs to zero at other times. And for those times where the output is zero the next stage in the pipeline shouldn't even be looking at those values. But I want to confirm it under simlation.
So I tried setting the outputs to 'U' or 'X' during the times they dont represent data and these show up in the simulator as orange or red, but if I force them to be erroneously sampled the bad values dont propagate. So it seems like neither U nor X are what I want. Without changing the consumers of these (e.g. calling is_x(..) in hundreds of places) is there any easy way to poison those values when running under the simulator.
If it matters, this is on a Spartan7 based Arty board with the free version of Vivado.
I need to draw a logic circuit using this K map.. but how can I represent all the other inputs on the circuit? I get (not)B as the answer.. but how should I show A C and D in the circuit?
You can either just place them in and have an open ended wire connected to nothing, or just don't include them. They have no relevance to the output of the circuit.
Since the K-Map brings the circuit into simplest form, its irrelevant where A, C, and D go. The K-map shows that, regardless of these variables, the simplest result will always be ~B. So, just put them as open wires or don't even include them. Doesn't really matter
Is it possible to make an arbitrary logic circuit using only single bit gates (Single input, single output) and some multiple bit gates (n bits in m bits out where n and m are any integers) which must be in a fixed position.
Or to ask the question another way:
Presume there exists a circuit which has some multiple bit gates in some fixed locations and many empty spaces where other gates may be inserted.
Would I be able to make an arbitrary program if I choose to only put in single input, single output logic gates in these empty places?
Would I require that the original circuit with fixed gates is infinitely large or exponentially bigger than the normal circuit for the same piece of logic?
Thanks in advance
Responding to myself incase others read this - Yes, this is universal.
Any 2-bit-input/1-bit-output gate may be constructed by using two 1-bit-input/1-bit-output gates in two predefined places.
From here universality follows.
Is there a logic gate or combination of logic gates that gives the following? If not, is there something that gives the following on Labview
Input: 00, 01 , 10 , 11
Output respectively: 0,1,0,0
I think its unlikely because distinguishing a 1 and 0 with a 0 and 1 doesn't seem to be possible at face value except if its a special gate.
It seems to me like what you want is (NOT A) AND (B). If you can't figure out how to do that in LabVIEW then you seriously need to take a step back and start with some basic tutorials, possibly even go to a proper course. You might also want to look at some more general computer science and programming courses.
You can do a lot with the Compound Arithmetic node.
I am taking a course on models of computation and currently we are doing finite state machines. One my tasks is to draw out a FSM that performs division of 3; to simplify the model the machine only accepts numbers multiple of 3. I am not sure how this exactly works, especially since I imagine FSM putting out only single binary values. Could you guys give examples (division by 2 or 4) or hints on how to approach this?
This is what you need, I think (sorry about the bad picture). The 'E' represents epsilon/lambda/no-output. The label of the edges denotes 'input/output'. For each symbol read there is also a corresponding output which may be lambda (no output).