This question already has answers here:
What do the makefile symbols $# and $< mean?
(6 answers)
Closed 6 years ago.
In some .mak files I see lines like:
$(CC) $[# $(CFLAGS) $(OFLAGS) $(DFLAGS)
I know that the $ sign means the value of the variable... But what is $[# (where there is no variable)?
Other examples: $[* , $^#
And $# $< in this answer, in the lines:
$(ODIR)/%.o: $(SDIR)/%.cpp
$(CC) -c $(INC) -o $# $< $(CFLAGS)
Now I know that the last two lines mean to create the .o files in ODIR directory and the .c files in SDIR directory. But what's the essential meaning of $# $<?
I couldn't find anything except these apache-related results as examples, with no explanation.
These are automatic variables as described here : GNU make : Automatic variables
Also see this thread : What do the makefile symbols $# and $< mean?
Related
This question already has answers here:
Getting make to create object files in a specific directory
(3 answers)
Closed 4 years ago.
In my project i have directory structure /libs and /src. I want to create makefile where main has dependency in /libs. ie. header file is in the /libs. I have used the following
#Compiler to use
CC=gcc
#Compiler flags to use
CFLAGS=-c -Wall
BUILD = ./build
SRC = ./src
LIBS = ./libs
SOURCES = $(SRC)/main.c $(SRC)/SmallComponent1.c $(SRC)/SmallComponent2.c $(LIBS)/ExtLib.c
OBJECTS = $(SOURCES: .c=.o)
EXECUTABLE = $(BUILD)/appl.exe
all: $(OBJECTS) $(EXECUTABLE)
$(BUILD):
mkdir $(BUILD)
$(EXECUTABLE) : $(OBJECTS)
$(CC) $(OBJECTS) -o $#
.c.o:
$(CC) $(CFLAGS) -I$(LIBS) $< -o $#
phony: clean
clean:
rm $(BUILD)/*.o $(BUILD)/appl.exe
Questions are: how can i create /build if not exist? and how to include external .h in the $(CC) $(CFLAGS) -I$(LIBS) $< -o $#, because -I$(LIBS)
does not work and i got following error ./src/main.c:4:20: fatal error: ExtLib.h: No such file or directory
To create the build directory before it is needed use an order-only prerequisite (OOP) and use the -p option of mkdir to avoid getting an error if it exists already (it should not be needed because of the OOP but it is always better to use this option in Makefiles):
$(BUILD):
mkdir -p $#
$(EXECUTABLE) : $(OBJECTS) | $(BUILD)
$(CC) $(OBJECTS) -o $#
For your other problem we need some more information; as you describe it it is not reproducible. Try maybe to provide an MCVE.
This question already has answers here:
In gnu make, can the prerequisites in a static pattern rule have different suffixes
(3 answers)
Closed 4 years ago.
Suppose I have three source files: file3.c, file2.c, file3.s which are all not of the same extension. I want to compile it into object files: file1.o, file2.o, file3.o which are of the same pattern.
OBJ = file1.o file2.o file3.o
all: $(OBJ)
#Here I am in the stuck
$(OBJ) : %.o : %.c #or %.s
$(CC) $(CFLAGS) -c $< -o $#
How to do this using pattern rules in GNU make?
The recipe for generating .o files can be made common for both .c and .s files this way:
OBJ = file1.o file2.o file3.o
.PHONY: all
all: $(OBJ)
.SECONDEXPANSION:
%.o: $$(wildcard $$*.c) $$(wildcard $$*.s)
$(CC) $(CFLAGS) -c $< -o $#
The prerequisite, which may end with .c or .s, is determined by secondary expanding the stem (i.e.: $*) and the wildcard built-in function for the filenames resulting from concatenating the stem with the corresponding "extensions" .c and .s.
The "or" is implemented by taking advantage of the fact that the wildcard built-in function is expanded to nothing (as opposed to be expanded to the provided pattern, like the Bash shell does) if the pattern is not matched (i.e.: if there is no filename that matched the pattern provided to wildcard).
I'm trying to figure out some differences in makefiles and what some of the code does. Below are some of the different items that I'm trying to address.
CC vs $(CC)
CP vs $(CP)
LD vs $(LD)
-Wl
This line of code. Is it setting a target of .o files to .c files in the first line? I understand the second line sets flags for compiling, but I don't quite understand the notation at -c $< -o *.o. -c is a flag to generate the object file, $< is the name of the prerequisite(don't really understand this), and -o I'm not certain of.
$(libSup)/%.o : %.c
$(MINGW_CC) $(ADDED_CFLAGS) $(EXTRA_INCLUDE) -c $< -o $(libSup)/$*.o
This question already has answers here:
What do the makefile symbols $# and $< mean?
(6 answers)
Closed 7 years ago.
Here's my sample makefile content:
CC=g++
CFLAGS=-c -Wall
...
$(CC) $(CFLAGS) $< -o $#
What does the $< mean here?
Read the documentation of GNU make. It is explained in the automatic variable section.
$<
The name of the first prerequisite. If the target got its recipe from an implicit rule, this will be the first prerequisite added by the implicit rule
I'm having troubles with my Makefile :-(
I have a mix of assembly and C sourcecode that I need to link together. I need different build-instructions for those two types. Since both the assembler and C compiler output *.o files, I cannot use the general %.o:%.c construction often found in example Makefiles
This what I'm trying now:
Get a list of all C files and their resulting output files:
C_SRCFILES := $(shell find $(SRCDIRS) -type -f -name "*.c")
C_OBJFILES := $(patsub %.c,%.o,$(C_SRCFILES))
Get a list of all asm files and their resulting output files:
A_SRCFILES := $(shell find $(SRCDIRS) -type -f -name "*.asm")
A_OBJFILES := $(patsub %.asm,%.o,$(A_SRCFILES))
When I echo those vars to the screen, they seem to be correct, but how I do define my targets now?
I tried something like this
$(A_OBJFILES): ($A_SRCFILES)
$(AS) $(AFLAGS) -o $# $*
$(C_OBJFILES): ($C_SRCFILES)
$(CC) $(CFLAGS) -c -o $# $*
all: $(A_OBJFILES) $(C_OBJFILES)
$(LD) $(LDFLAGS) $(A_OBJFILES) $(C_OBJFILES) -o $(TARGET_OUTPUT)
but ofcourse, this doesn't work...
Any suggestions?
First problem: a misplaced parenthesis or two.
$(A_OBJFILES): ($A_SRCFILES)
Notice that you have the $ inside the ( in ($A_SRCFILES). Make expands $A, which is nothing, and things go downhill. I think you meant $(A_SRCFILES), and the same thing in the other rule.
Second problem: I don't know the syntax of the assembler, but the syntax of the compiler command is wrong:
$(CC) $(CFLAGS) -c -o $# $*
The variable $* is nothing if we're not in a pattern rule, which we're not (yet). And anyway, if we were in a pattern rule and you were trying to build foo.o, this command would look for the source file foo, and there's no such file. Do it this way:
$(CC) $(CFLAGS) -c -o $# $<
Third problem: each object file depends on all source files (in each rule). Try this instead:
$(A_OBJFILES): %.o : %.asm
...
$(C_OBJFILES): %.o : %.c
...
(Now it's a pattern rule.)
Fourth problem: a lot of redundancy in the last rule. Change it to this:
all: $(A_OBJFILES) $(C_OBJFILES)
$(LD) $(LDFLAGS) $^ -o $(TARGET_OUTPUT)
or better still:
all: $(TARGET_OUTPUT)
$(TARGET_OUTPUT): $(A_OBJFILES) $(C_OBJFILES)
$(LD) $(LDFLAGS) $^ -o $#
Since both the assembler and C compiler output *.o files, I cannot use the general %.o:%.c construction often found in example Makefiles
Sure you can:
%.o : %.c
# commands to make .o from a corresponding .c
%.o : %.asm
# commands to make .o from a corresponding .asm