Signed Addition overflow in VHDL - vhdl

Question

I tried to implement and addition of two signed numbers. The first one is 32 bit and the second one is also 32 bit, but correspond the addition of the earlier operation. The code VHLD is below :
Entity Sum_Position is
port
(
Clk: in std_logic;
Reset: in std_logic;
Raz_position: in std_logic;
Position_In: in std_logic_vector(31 downto 0);
Position_Out: out std_logic_vector(31 downto 0)
);
end Sum_Position;
Architecture Arch_position of sum_Position is
-- create locale signals
signal position_before: signed (31 downto 0):= (OTHERS => '0');
-- both signals have one more bit than the original
signal Position_s : SIGNED(Position_In'length downto 0):= (OTHERS => '0');
signal Position_Before_s : SIGNED(Position_In'length downto 0):= (OTHERS => '0');
signal Sum_Pos_s : SIGNED(Position_In'length downto 0):= (OTHERS => '0');
Begin -- begin of architecture
-- convert type and perform a sign-extension
Position_s <=SIGNED(Position_In(31) & Position_In);
Position_Before_s<=resize(signed(position_before), Position_Before_s'length);
Sum_of_position: process(Clk, Reset)
begin
IF (Reset='0') THEN -- when reset is selected
-- initialize all values
Sum_Pos_s<= (OTHERS => '0');
ELSIF (Clk'event and Clk = '1') then
-- addition of two 33 bit values
Sum_Pos_s <= Position_s + Position_Before_s;
END IF;
end process Sum_of_position;
-- resize to require size and type conversion
position_before <= (OTHERS => '0') WHEN Raz_position='1' else
signed(resize(Sum_Pos_s, position_before'length));
-- Resize and output the result
Position_Out <= (OTHERS => '0') WHEN Raz_position='1' else
std_logic_vector(resize(Sum_Pos_s, Position_Out'length));
end Arch_position;
But, i have overflow because the result is very strange. Can you please suggest me a solution?
Best regards;

Answer 1

First of all your code is quite unclear.
Secondly, there is no reason for position_before(_s) to be asynchronous, it should be clocked, e.g. (summarized):
begin
IF (Reset='0') THEN -- when reset is selected
-- initialize all values
Sum_Pos_s<= (OTHERS => '0');
ELSIF (Clk'event and Clk = '1') then
Position_Before_s <= Sum_Pos_s
Sum_Pos_s <= Position_s + Position_Before_s;
END IF;
end process Sum_of_position;
Thirdly, the answer to your question. You pass floats to your VHDL engine. Interprete them as signed and add them. You should look at IEEE754 floats. There is a fixed field for the sign bit, one for the exponent and one for the mantissa. You can't just add everything up.
Step 1 is to express both on the same exponent basis. Then add the adjusted mantissas and keep the exponent. Then rescale the mantissa for the most significant bit to correspond to 0.5.
What you to is the following:
0.4 + 40 = (0.1) * 4 + (10) * 4
mantissas are both 4
exponents are -1 and 1. without fields overflowing, your result becomes an exponent of 0 and a mantissa of 8, so 8.

Answer 2

Most modern VHDL tools have Integer types (signed and unsigned).
These are usually 32 bits wide unless you use the Range modifier.
I suggest you consider using integers rather than std_logic_vector.
You can convert between types like casts in C.
This is my favourite diagram on casting/ converting VHDL types. I have printed it out and put it on my wall http://www.bitweenie.com/listings/vhdl-type-conversion
A page in integers in VHDL http://vhdl.renerta.com/mobile/source/vhd00039.htm