I'm trying to migrate an existing C/C++ CUDA project into Nsight Eclipse. I'm using a manually written makefile to build the project, however I am getting the following error:
#error -- unsupported GNU version! gcc versions later than 4.9 are not supported!
I previously had this error when I was using just a makefile outside of Nsight, however I fixed it by creating symlinks to gcc-4.9 and g++-4.9 in /usr/local/cuda-7.5/bin. This does not work for Nsight.
Here is my makefile (NOTE: I've set the CUDA_HOME environment variable inside Nsight):
NVCC := nvcc
MODULES := FA_kernels FD_kernels MEM_kernels MOD_kernels .
SRC_DIR := $(MODULES)
BUILD_DIR := $(addprefix build/,$(MODULES))
SRC := $(foreach sdir,$(SRC_DIR),$(wildcard $(sdir)/*.cu))
OBJ := $(patsubst %.cu,build/%.o,$(SRC))
HEADERS := headers $(CUDA_HOME)/include $(CUDA_HOME)/samples/common/inc
INCLUDES := $(addprefix -I,$(HEADERS))
build/%.o: %.cu
$(NVCC) $(INCLUDES) -c $< -o $#
.PHONY: all checkdirs clean
all: checkdirs build/lem
build/lem: $(OBJ)
$(NVCC) $^ -o $# -lgdal
checkdirs: $(BUILD_DIR)
$(BUILD_DIR):
#mkdir -p $#
clean:
#rm -rf build
Is there a way I can force Nsight to use gcc-4.9 and g++-4.9?
I assume based on your question text you have imported this as a makefile project.
In that case, one option would be to change the first line in your makefile to something like this:
NVCC := nvcc -ccbin /path/to/gcc
You can read more about this option in the nvcc documentation
This would effect this change just for this project/makefile, not for all projects or all of eclipse/nsight
Related
I have a Makefile that works correctly, but now I want to modify it so that I can build two different executables (i.e. client.exe, server.exe). In my directory, I have a client.cpp and a server.cpp, each of which has a main function. I know I can't build an executable with more than one main function. Ultimately, I want to be able to build an executable (client.exe or server.exe) using 'make client', 'make server', or something to that effect.
I have seen similar questions on this website, but all of the solutions I have seen assume that the number of source files will not change. Take for example this solution: Makefile to compile multiple C programs? Or this question: How can I configure my makefile for debug and release builds?
I do not want to have to update my Makefile every time I add a new source file.
How can I modify my Makefile so that I build two different executables?
SRC_DIR := src
OBJ_DIR := obj
BIN_DIR := bin
EXE := $(BIN_DIR)/client.exe
SRC := $(wildcard $(SRC_DIR)/*.cpp)
OBJ := $(subst $(SRC_DIR),$(OBJ_DIR),$(SRC:.cpp=.o))
DEP := $(OBJ:.o=.d)
.PHONY: clean
all: $(EXE)
CXX := g++
CPPFLAGS := -I$(PWD) -MMD -MP
CXXFLAGS := -std=c++17
LDFLAGS := -L /usr/lib/x86_64-linux-gnu
CFLAGS := -Wall
$(EXE): $(OBJ) | $(BIN_DIR)
$(CXX) $(LDFLAGS) $^ -o $#
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp | $(OBJ_DIR)
$(CXX) $(CPPFLAGS) $(CFLAGS) $(CXXFLAGS) -c $< -o $#
$(BIN_DIR) $(OBJ_DIR):
mkdir -p $#
clean:
#$(RM) -rv $(BIN_DIR) $(OBJ_DIR)
-include $(DEP)
I have tried to exclude either the client.cpp or server.cpp file depending on which command I use (e.g. 'make client' or 'make server'). But I reached a dead end since I don't know how to make a rule that excludes one file.
SRC := $(filter-out $(SRC_DIR)/client.cpp, $(wildcard $(SRC_DIR)/*.cpp))
SRC := $(filter-out $(SRC_DIR)/server.cpp, $(wildcard $(SRC_DIR)/*.cpp))
Simply build two different lists of object files for your two executables:
...
EXE := $(patsubst %,$(BIN_DIR)/%.exe,client server)
...
CLIENT_OBJ := $(filter-out $(OBJ_DIR)/server.o,$(OBJ))
SERVER_OBJ := $(filter-out $(OBJ_DIR)/client.o,$(OBJ))
.PHONY: all client server
all: $(EXE)
client: $(BIN_DIR)/client.exe
server: $(BIN_DIR)/server.exe
$(BIN_DIR)/client.exe: $(CLIENT_OBJ)
$(BIN_DIR)/server.exe: $(SERVER_OBJ)
$(EXE): | $(BIN_DIR)
$(CXX) $(LDFLAGS) $^ -o $#
...
I have the following makefile:
compiler := g++
flags := -Wall -Wextra -Wpedantic -Werror -O2 -march=native
libs := sqlite3
build_dir := build
debug_dir := debug
source_dir := src
object_dir := obj
include_dir := include
objects := main.o politician.o data_base.o exceptions.o input.o
# Prepend object_dir/ to every object
objects := $(patsubst %, $(object_dir)/%, $(objects))
dependencies := data_base.hpp exceptions.hpp politician.hpp input.hpp CLI11.hpp
# Prepend include_dir/ to every dependency
dependencies := $(patsubst %, $(include_dir)/%, $(dependencies))
executable := politician
# Don't remove object files when finished
.SECONDARY: $(objects)
.PHONY: all
all: $(build_dir)/$(executable) | $(build_dir)
.PHONY: debug
debug: flags += -g
debug: $(debug_dir)/$(executable) | $(debug_dir)/
%/$(executable): $(objects)
$(compiler) $(flags) -l $(libs) $^ -o $#
$(object_dir)/%.o: $(source_dir)/%.cpp $(dependencies) | $(object_dir)/
$(compiler) $(flags) -I $(include_dir) -c $< -o $#
%/:
mkdir -p $#
.PHONY: clean
clean:
rm -f $(objects)
.PHONY: clean-all
clean-all:
rm -f $(objects) $(build_dir)/$(executable) $(debug_dir)/$(executable)
It's expected that, after running make clean, make all would recompile everything (because the executable depends on the objects and they are not present anymore), but it's not what's happening: instead I get make: Nothing to be done for 'all'.
What's causing this behavior?
This happens because you are using a chain of pattern rules.
Consider a simple example:
all: build/politician
build/politician: main.o
whatever...
main.o: src/main.cpp
whatever...
If you run make, it will build main.o, then build/politician. If you then delete main.o and again run make, again it will build main.o and build/politician.
Now change two of the rules into pattern rules:
all: build/politician
%/politician: main.o
whatever...
%.o: src/%.cpp
whatever...
Now the first time you run make, it will once again build main.o and then build/politician. But then when you delete main.o and again run make, it will report "Nothing to be done for 'all'" and do nothing. This is because main.o is now an intermediate file, and according to the manual:
If an ordinary file b does not exist, and make considers a target that depends on b, it invariably creates b and then updates the target from b. But if b is an intermediate file, then make can leave well enough alone. It won’t bother updating b, or the ultimate target, unless some prerequisite of b is newer than that target or there is some other reason to update that target.
Following this question and my answer and its comments I have a doubt.
What is the proper way to reference dependencies in a Makefile?
Let me give an example considering this file:
CXX = g++
CXXFLAGS = -stdlib=libc++ -std=c++17
WARNING := -Wall -Wextra
PROJDIR := .
SOURCEDIR := $(PROJDIR)/
SOURCES := $(wildcard $(SOURCEDIR)/*.cpp)
OBJDIR := $(PROJDIR)/
OBJECTS := $(patsubst $(SOURCEDIR)/%.cpp,$(OBJDIR)/%.o,$(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.cpp,$(OBJDIR)/%.d,$(SOURCES))
# .PHONY means these rules get executed even if
# files of those names exist.
.PHONY: all clean
all: main
clean:
$(RM) $(OBJECTS) $(DEPENDS) main
clean:
$(RM) $(OBJECTS) $(DEPENDS) parking
# Linking the executable from the object files
main: $(OBJECTS)
$(CXX) $(WARNING) $(CXXFLAGS) $^ -o $#
#include your dependencies
-include $(DEPENDS)
#create OBJDIR if not existin (you should not need this)
$(OBJDIR):
mkdir -p $(OBJDIR)
$(OBJDIR)/%.o: $(SOURCEDIR)/%.cpp Makefile | $(OBJDIR)
$(CXX) $(WARNING) $(CXXFLAGS) -MMD -MP -c $< -o $#
I can do DEPENDS := $(patsubst $(SOURCEDIR)/%.cpp,$(OBJDIR)/%.d,$(SOURCES)) but also DEPENDS := $(wildcard $(OBJDIR)/*.d): can't I?
If I delete a source file before running make clean the correspondent dependency file remains. In the second case it will be removed with the next make clean while in the first it will not. However if I do not run make clean dependencies not related to the sources might be included.
What is the best way to reference dependencies in a Makefile? Should I use two variables, one to run clean and the other for include?
I'm trying to get SFML to work with Eclipse but I'm unsuccessfull(running MinGW 3.17-2 and gcc 4.8.1)
The file is compiled but when I try to run it I get the following error:
Looking in my MinGW\bin folder I can only see a libgcc_s_dw2-1.dll file and after some searching it appears that the dll asked for is for a 64-bit version? My OS is 64 bit but both MinGW and the SFML libraries all 32-bit.
How can I resolve this?
Makefile:
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(CC_DEPS)),)
-include $(CC_DEPS)
endif
ifneq ($(strip $(C++_DEPS)),)
-include $(C++_DEPS)
endif
ifneq ($(strip $(C_UPPER_DEPS)),)
-include $(C_UPPER_DEPS)
endif
ifneq ($(strip $(CXX_DEPS)),)
-include $(CXX_DEPS)
endif
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
ifneq ($(strip $(CPP_DEPS)),)
-include $(CPP_DEPS)
endif
endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
# All Target
all: Test
# Tool invocations
Test: $(OBJS) $(USER_OBJS)
#echo 'Building target: $#'
#echo 'Invoking: Cross G++ Linker'
g++ -L"F:\Libs\SFML-2.2\lib" -o "Test" $(OBJS) $(USER_OBJS) $(LIBS)
#echo 'Finished building target: $#'
#echo ' '
# Other Targets
clean:
-$(RM) $(CC_DEPS)$(C++_DEPS)$(EXECUTABLES)$(OBJS)$(C_UPPER_DEPS)$(CXX_DEPS)$(C_DEPS)$(CPP_DEPS) Test
-#echo ' '
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets
objects.mk:
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS := -lsfml-graphics-d -lsfml-system-d -lsfml-window-d
sources.mk:
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
C_UPPER_SRCS :=
CXX_SRCS :=
C++_SRCS :=
OBJ_SRCS :=
CC_SRCS :=
ASM_SRCS :=
C_SRCS :=
CPP_SRCS :=
O_SRCS :=
S_UPPER_SRCS :=
CC_DEPS :=
C++_DEPS :=
EXECUTABLES :=
OBJS :=
C_UPPER_DEPS :=
CXX_DEPS :=
C_DEPS :=
CPP_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
. \
subdir.mk
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
CPP_SRCS += \
../main.cpp
OBJS += \
./main.o
CPP_DEPS += \
./main.d
# Each subdirectory must supply rules for building sources it contributes
%.o: ../%.cpp
#echo 'Building file: $<'
#echo 'Invoking: Cross G++ Compiler'
g++ -I"F:\Libs\SFML-2.2\include" -O0 -g3 -Wall -c -fmessage-length=0 -std=c++11 -MMD -MP -MF"$(#:%.o=%.d)" -MT"$(#:%.o=%.d)" -o "$#" "$<"
#echo 'Finished building: $<'
#echo ' '
Due to the way name mangling and non-standardized ABI work in C++, there is unfortunately about no compatibility between different versions of compilers. In your case, you're even trying to use a library compiled with a compiler from a different "MinGW" project than your current compiler is. But even if you were using the same "type" of compiler, C++ libraries usually aren't reusable across minor or patch versions.
First of I really recommend to not use the original MinGW project and rather go for a compiler based on the MinGW-w64 project. If you want reasons for that, you can ask Google, there are enough discussion about it.
Second you either need to pick a compiler that matches on of the SFML packages OR you need to build SFML yourself.
For the GCC 4.9.2 MinGW (DW2) - 32-bit package I used this compiler.
For the GCC 4.7.1 TDM (SJLJ) - 32-bit package I used the compiler that shipped with this Code::Blocks package.
For the GCC 4.8.1 TDM (SJLJ) - 32-bit package I used the compiler that shipped with this Code::Blocks package.
And third, if you want the latest development version of SFML using the latest compiler versions, you can check out my Nightly Builds.
I'm attempting to put together a makefile that will take source files from a directory (eg. src), compile them into object files in another directory (eg. build), and then take those files and create a static library from them in the main directory.
Here's my effort so far:
LIBNAME := test
LIBNAME := lib$(LIBNAME).a
CC = g++
CFLAGS := -O0 -Wall -g -fPIC
INCLUDE := include
SOURCE := src
BUILD := build
CPPFILES := $(foreach dir, $(SOURCE)/, $(notdir $(wildcard $(SOURCE)/*.cpp)))
OBJFILES := $(addprefix $(BUILD)/, $(CPPFILES:.cpp=.o))
all: $(LIBNAME) $(OBJFILES)
$(LIBNAME): $(OBJFILES)
ar rcs $(LIBNAME) $(OBJFILES)
.cpp.o:
$(CC) $(CFLAGS) -I$(INCLUDE) -c $< -o $#
clean:
rm -rf $(BUILD)
Which gives me this:
make: *** No rule to make target `build/point.o', needed by `libtest.a'. Stop
You seem do be requiring GNU make anyway (foreach function), so rewriting the old-style suffix rule .cpp.o to
$(BUILD)/%.o : $(SOURCE)/%.cpp
should do the trick. You might also try using the VPATH variable or the vpath directive, see the make manual for these.
In general, you might just tackle this problem with automake, which does most of this stuff for you.