First of all, sorry for bad English since my English skill is not that good...
Before the question, I want to explain my situation to help understanding.
I want to use EEPROM as a kind of counter.
The value of that counter would be increased very frequenty so I should consider endurance problem.
My idea is, write counter value on multiple address alternatively so cell wearing is reduced by N.
for example, if I use 5x area for counting,
Count 1 -> 1 0 0 0 0
Count 2 -> 1 2 0 0 0
Count 3 -> 1 2 3 0 0
Count 4 -> 1 2 3 4 0
Count 5 -> 1 2 3 4 5
Count 6 -> 6 2 3 4 5
...
So cell endurance can be extended by a factor of N.
However, AFAIK, for current NAND flash, data erase/write is done by a group of bytes, called block. So, if all the bytes are within single write/erase block, my method would not work.
So, my main question : Does erase/write operation of EEPROM of PIC is done by a group of bytes? or done by a single word or byte?
For example, if it is done by a group of 8-bytes, then I should make 8-byte offset between each counter value to make my method properly work.
Otherwise, if it is done by a byte or a word, I don't have to consider about spacing/offset.
From datasheet PIC24FJ256GB110 section 5.0:
The user may write program memory data in blocks of 64 instructions
(192 bytes) at a time, and erase program memory in blocks of 512
instructions (1536 bytes) at a time.
However you can overwrite individual block several times if you left the rest of block erased (bits are one) and the privius content rest the same. Remember: you can clear single bit in block only ones.
How much will decerease the data retention after 8 writes in to single FLASH block I don't know!
Related
I'm sorry if I made an error in posting this. Please let me know if I need to change anything.
I've received my computer architecture homework back and I missed this question. My professor's explanation didn't make sense to me, and I disagree with what he told me, so I am here asking what you guys think.
Here is the question:
A computer uses 16-bit memory addresses. Main memory is 512KB, and the cache is 1KB with 32B per block. Given each of the following mapping functions, calculate the number of bits in each field of the memory address.
Here is how I worked through the direct mapping part of the problem:
Cache memory: 1KB (2^10), 16-bit memory addresses (1 word = 2B) -> 1024B/2B = 512 words, 16 words per block (32B) -> 512/16 = 32 cache memory blocks.
Main memory: 512 KB (2^19), 16-bit memory addresses (1 word = 2B) -> 524288B/2B = 256K words, 16 words per block (32B) -> 256K/16 = 16384 or 16K main memory blocks.
I understand the word tag as such: 32B per block allows for 16 16-bit memory addresses per block. This (I believe) supports that: 1 word = 16 bits = 2 B -> 32B/2B = 16 words in each block. This equates to 2^4 = 4 bits for determining which word in the block, leaving 12 bits for tag and block bits in the memory address.
Now, in order to map 16K main memory blocks directly into 32 cache memory blocks, there will have to be 512 main memory blocks mapped to each cache memory block. So 512/16K blocks per 1/32 blocks.
Here is where I am confused. Doesn't this require 9 tag bits, as 2^9 = 512 (main memory blocks possibly mapped into one cache memory block)?
For the block bits, which point to a particular block in the cache, this requires 5 bits. 2^5 = 32, blocks in cache memory.
This would require 18 bits in the memory address.
Here is my professor's answer for this question:
2^5 = 32 -> 5 Word bits
(1KB)/(32B) = 32 blocks -> 5 Block bits
16 – 5 – 5 = 6 Tag bits
I did not realize I could simply subtract the required block and word bits to get the tag bits. But it still doesn't make sense to me. 2^6 = 64 blocks per cache block. 64*32 gives 2048. I can't wrap my head around this. Can someone please help?
Okay, the terminology that i learnt is slightly different but the principal should be the same for this explanation.
So cache will have multiple sets (sort of like a cell). And each set will have 1 cache line (containing 1 block of data) or multiple cache lines (each contain 1 block of data) (direct mapping or n-associativity mapping).
In mapping the main memory blocks to the cache, the main memory address (16 bit) is divided into 3 fields: tag, index bits and offset bits. A memory cell is 1 byte and a block is made up of a few cells
Offset bits are used to access the individual bytes of a memory block. Think of it as the offset on top of the block base address to get the byte you want (i assume your memory should be byte-addressable rather than word-addressable as it doesn't make sense to access 2B word as this would be inflexible) And here your prof/textbook call it as word bit. Hence if a block has 32 Bytes, there would be log2(block size) = 5 bits needed to access the individuals cells in the mapped block.
Index bits (in direct mapped cache is called block bits too as the number of set is the same as the number of blocks in the cache) is used to identify which set/cache line/ cache block that the main memory block is mapped to the cache. There are 1KB/32B = 32 cache blocks in the cache. As direct mapping is used, each set contain only 1 cache block and therefore there will be 32 set in this cache. Thus to access the correct set in cache, 5 bits is needed and therefore index bits = 5 bits
Tag is a name to determine if the data block in cache is the correct one we are looking one from the main memory. As the address of main memory is 16 bit and we already know index and offset fields, it is easy to deduce that tag will need 16 - 5 - 5 6 bits. How we determine the tag is not really a concern as the block size and cache size (and hence no. of sets in cache is given here).
I have this machine code for an accumulator architecture.
The architecture is eight-bit; the instruction encoding looks like
the real machine code is for instruction one for example is : 001 1 0001, 001 means LOAD, 1 tells us that is a value, and 001 is the decimal 1 so its LOAD #1
0---LOAD #1
1---STORE 15
2---LOAD #0
3---EQUAL #4
4---JUMP #6
5---HALT
6---LOAD 3
7---SUB #1
8---STORE 3
9---LOAD 15
10--ADD 15
11--STORE 15
12--JUMP #2
13-- 000 0 0000
14-- 000 0 0000
15-- 000 0 0000
I have to find what will be in memory cell 15 when the program stops.
But if you jump to instruction 2, this means that accumulator would have the value 0 which will never be equal to 4 and the program will just run as endless loop, right?
And what does the STORE 3 do, if memory cell 3 is empty? Does it mean that when a memory cell is empty its value is number 0?
I cannot proceed more without answering these two questions
I'm assuming that this is for a n accumulator architecture, and I'm having to make a number of assumptions about that architecture. You really need to describe more of how your CPU works to make this an answerable question.
Yes, at #3, the accumulator will always be 0.
And yes, if instruction #3 never changes, then 0 will never equal 4 and the program will loop for ever.
However, when you store to memory cell 3, I wthink that you end up replacing the instruction at cell 3 with what is in the accumulator now.
So, the interesting question is what happens when you subtract 1 from the instruction representation of equal #4.
That depends on yoru specific architecture, but my strong guess is that you get equal #3 and store that in cell 3.
That should be enough for you to walk through and figure out when your loop terminates and what is in cell 15.
To start off, the first cache has 16 one-word blocks. As an example I will use 0x03 memory reference. The index has 4 bits (0011). It is clear that the bits equal 3mod16 (0011 = 0x03 = 3). However I am getting confused using this mod equation to determine block location in a cache with offset bits.
The second cache has a total size of eight two-word blocks. This means that there is 1 offset bit. Since there are now 8 blocks, there are only 3 index bits. As an example, I will take the same memory reference of 0x03. However now I am having trouble mapping to the block using the mod equation I used before. I try 3mod8 which is 3, however in this case, since there is an offset bit, the index bits are 001. 001 is not equal to 3 so what did I do wrong? Does mod not work when there are offset bits? I was under the impression that the mod equation would always equal the index bits.
Its all in the address. You get the address, then mask off number of bits from the end, for following reasons.
Number of words in the cacheline. If you've got 2 word cacheline (take a bit out, 4 word - 2 bts etc)
Then how many cacheline entries you have. (If is a 1024 cacheline, you takeout 10 bits. This 10 bits is your index, remaining bits are for your Tag)
Now, you also need to consider 'WAY' as well. If its a direct mapped cache, above applies. If its a 2 way set associative cache, you dont have 1024 lines, what you have a 512 blocks with each having 2 lines in them. Which means you only need 9 bits to determine the index of the block. If its 4 way, you've got 256 blocks with 4 lines in them, meaning you only need 8 bits for your index.
In a set associative cache, index are there to choose a block, once a block is chosen, use can use a policy like LRU to fill an entry in case of a cache miss. Hits are determined by comparing the tag in the selected block.
Bottom line, block location is not determined by the address, only a block is selected by the address and thereafter its Tag comparison to find the data.
We got a cache given with 8 frames and it's directly mapped. Following access sequence on main memory blocks has been observed:
2 5 0 13 2 5 10 8 0 4 5 2
Count the hit rate of this organized cache.
Solution:
I understand how and why the numbers are placed in the table like that. But I don't understand why 2 and 5 have been bold-printed and why we got hit rate of 17%.
This has been solved by our professor but I don't understand it completely.
Like was mentioned by #Margaret Bloom in the comments, the numbers in bold refer to cache-hits. Non-bold refer to cache misses.
You might understand it better by using this simulator: cachesimulator.com
The Simulator works with WORD-instructions only, so a little conversion of your assignment need to be made in order to simulate it:
cache-size: 32 bytes (8 rows)
block-size: 4 bytes (one word per row)
associativity: 1 (direct-mapped cache)
replacement algorithm: LRU
memory size: (any number larger than (14*4) works) for example: 1024
Now since the simulator works with WORD-instructions you need to convert your access sequence by multiplying each number by 4, also, in the simulator you enter addresses in hexadecimal so after you have multiplied by 4 you convert to hexadecimal, then you get:
8 14 0 34 8 14 28 20 0 10 14 8
In the simulator you enter instructions on the form:
<operationtype><space><register><space><address>
In your case the operationtype is LOAD and the register does'nt matter. So you can use any register, for example:
LOAD 1 8
LOAD 1 14
LOAD 1 0
LOAD 1 34
LOAD 1 8
LOAD 1 14
LOAD 1 28
LOAD 1 20
LOAD 1 0
LOAD 1 10
LOAD 1 14
LOAD 1 8
Enter the instructions above in the text-area of the simulator and click run. You can then see the cache hits and misses in real-time and when the simulation is finnished you can analyze the results by looking at the content of the cache memory and the list of instruction-results. You can view the main-memory address that each element in the cache refers to by hovering over it.
I understand how and why the numbers are placed in the table like that.
So you understand which how addresses map to cache lines, and that the vertical axis is time.
But I don't understand why 2 and 5 have been bold-printed and why we got hit rate of 17%.
The table entries are bold (cache hit) when the previous access to the same cache line was to the same address. A different address that maps to the same cache line causes a cache miss (evicting the old contents).
Visually / graphically: look vertically upwards in the same column to see which data is currently hot in the cache line.
Obviously once you know how many cache hits there were, calculating the hit rate is easy.
Normally you should just ask your professor extremely basic questions like this. However, your diagram was really easy to understand, so it made this trivial question easy to understand and answer.
On my assignment we have 2 questions: we have a 2-way set associative cache. The cache has four sets in total. Main memory consists of 4K blocks of 8 words each and word addressing is used.
Part a) ask to demonstrate the address format, which I've solved to be word = 3 bit set =2 bit and field = 7 bit. The problem im having is in part b):
Compute the hit ratio for a program that loops 3 times from location 8 to location 51. In other words, think of this as an assembly language program that runs from the opcode at location 8 to the opcode at location 51m then loops back to location 8. It does three such iterations in total.
Now to my understanding after the research I've done there's a standard normally some sort of speed or hit rate that is given? I was wondering how do i calculate the hit ratio if i don't know a miss rate, a miss penalty a cache speed or anything?
I think we're in the same class lol I have the exact same question on assignment due tonight.. Anyway I did some research and found this answer to a similar question on chegg:
a. Given that memory contains 2K blocks of eight words.
2K can be distributed as 2K * 23 = 211* 23 = 214 so we have 14-bit addresses with 9 bits
in the tag field, 2 bits in the set field and 3 in the word field
b. First iteration of the loop:
→ Address 8 is a miss, then entire block brought into Set 1.9-15 are then hits.
→ 16 is a miss, entire block brought into Set 2, 17-23 are hits.
→ 24 is a miss, entire block brought into Set 3, 25-31 are hits.
→ 32 is a miss, entire block brought into Set 0, 33-39 are then hits.
→ 40 is a miss, entire block brought into Set 1 41-47 are hits.
→ 48 is a miss, entire block brought into Set 2, 49-51 are hits.
For the first iteration of the loop, we have 6 misses, and 5*7 + 3 hits, or 38 hits.
On the remaining iterations, we have 5*8+4 hits, or 44 hits each,for 88 more hits.
Therefore, we have 6 misses and 126 hits, for a hit ratio of 126/132, or 95.45%.
Hope this helps, good luck!